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Zhiyi Yu
Zhiyi Yu
Associate Professor of Microelectronics, Fudan University
Verified email at fudan.edu.cn
Title
Cited by
Cited by
Year
A 167-processor computational platform in 65 nm CMOS
DN Truong, WH Cheng, T Mohsenin, Z Yu, AT Jacobson, G Landge, ...
IEEE Journal of Solid-State Circuits 44 (4), 1130-1144, 2009
3032009
An asynchronous array of simple processors for DSP applications
Z Yu, M Meeuwsen, R Apperson, O Sattari, M Lai, J Webb, E Work, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
1142006
AsAP: An asynchronous array of simple processors
Z Yu, MJ Meeuwsen, RW Apperson, O Sattari, M Lai, JW Webb, EW Work, ...
IEEE Journal of Solid-State Circuits 43 (3), 695-705, 2008
1082008
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
RW Apperson, Z Yu, MJ Meeuwsen, T Mohsenin, BM Baas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (10 …, 2007
922007
A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling
D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ...
2008 IEEE Symposium on VLSI Circuits, 22-23, 2008
862008
High performance, energy efficiency, and scalability with GALS chip multiprocessors
Z Yu, BM Baas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (1), 66-79, 2008
472008
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array
P Ou, J Zhang, H Quan, Y Li, M He, Z Yu, X Yu, S Cui, J Feng, S Zhu, J Lin, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
462013
AsAP: A fine-grained many-core platform for DSP applications
B Baas, Z Yu, M Meeuwsen, O Sattari, R Apperson, E Work, J Webb, ...
IEEE Micro 27 (2), 34-45, 2007
432007
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms
Z Yu, K You, R Xiao, H Quan, P Ou, Y Ying, H Yang, X Zeng
2012 IEEE International Solid-State Circuits Conference, 64-66, 2012
422012
A scalable network-on-chip microprocessor with 2.5 D integrated memory and accelerator
SM PD, J Lin, S Zhu, Y Yin, X Liu, X Huang, C Song, W Zhang, M Yan, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (6), 1432-1443, 2017
372017
A low-area multi-link interconnect architecture for GALS chip multiprocessors
Z Yu, BM Baas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (5), 750-762, 2009
352009
Implementing tile-based chip multiprocessors with GALS clocking styles
Z Yu, B Baas
2006 International Conference on Computer Design, 174-179, 2006
322006
Parallelization of radix-2 Montgomery multiplication on multicore platform
J Han, S Wang, W Huang, Z Yu, X Zeng
IEEE transactions on very large scale integration (VLSI) systems 21 (12 …, 2013
292013
A 65 nm cryptographic processor for high speed pairing computation
J Han, Y Li, Z Yu, X Zeng
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 692-701, 2014
272014
An optimized mapping algorithm based on simulated annealing for regular NoC architecture
L Zhong, J Sheng, Z Yu, X Zeng, D Zhou
2011 9th IEEE International Conference on ASIC, 389-392, 2011
252011
Low-power multicore processor design with reconfigurable same-instruction multiple process
Z Yu, Z Yu, X Yu, N Liu, X Zeng
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (6), 423-427, 2014
222014
An FPGA-based hardware accelerator for traffic sign detection
W Shi, X Li, Z Yu, G Overett
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016
192016
A 16-core processor with shared-memory and message-passing communications
Z Yu, R Xiao, K You, H Quan, P Ou, Z Yu, M He, J Zhang, Y Ying, H Yang, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1081-1094, 2013
182013
Performance and power analysis of globally asynchronous locally synchronous multiprocessor systems
Z Yu, BM Baas
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006
182006
Model and physical implementation of multi-port PUF in 65 nm CMOS
Y Zhang, P Wang, Y Li, X Zhang, Z Yu, Y Fan
International Journal of Electronics 100 (1), 112-125, 2013
162013
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