| OpenCL-based FPGA design to accelerate the nodal discontinuous Galerkin method for unstructured meshes T Kenter, G Mahale, S Alhaddad, Y Grynko, C Schmitt, A Afzal, F Hannig, ... 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 34 | 2018 |
| Hardware solution for real-time face recognition G Mahale, H Mahale, A Goel, SK Nandy, S Bhattacharya, R Narayan 2015 28th International Conference on VLSI Design, 81-86, 2015 | 17 | 2015 |
| REFRESH: REDEFINE for Face Recognition using SURE Homogeneous Cores G Mahale, H Mahale, SK Nandy, R Narayan IEEE Transaction on Parallel and Distributed Systems, 2016 | 8 | 2016 |
| Windconv: A fused datapath cnn accelerator for power-efficient edge devices G Mahale, P Udupa, KK Chandrasekharan, S Lee IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 7 | 2020 |
| IKW: Inter-kernel weights for power efficient edge computing P Udupa, G Mahale, KK Chandrasekharan, S Lee IEEE Access 8, 90450-90464, 2020 | 7 | 2020 |
| Hardware architecture of bi-cubic convolution interpolation for real-time image scaling G Mahale, H Mahale, RB Parimi, SK Nandy, S Bhattacharya 2014 International Conference on Field-Programmable Technology (FPT), 264-267, 2014 | 6 | 2014 |
| Accelerating depthwise convolution and pooling operations on Z-first storage CNN architectures P Udupa, G Mahale, KK Chandrasekharan, S Lee 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 4 | 2020 |
| Vop: Architecture of a processor for vector operations in on-line learning of neural networks G Mahale, E Bhatia, SK Nandy, R Narayan 2016 29th International conference on VLSI design and 2016 15th …, 2016 | 3 | 2016 |
| Power-efficient hybrid traversal apparatus and method for convolutional neural network accelerator architecture GV Mahale, PP Udupa, KK Chandrasekharan, SH Lee US Patent App. 17/033,132, 2021 | 2 | 2021 |
| Eigen values and vectors computations on VIRTEX-5 FPGA platform cyclic Jacobi's algorithm using systolic array architecture GV Mahale, PP Bartakke IET Digital Library, 2011 | 2 | 2011 |
| Z-first reference neural processing unit for mapping winograd convolution and a method thereof GV Mahale, PP Udupa, KKC HARAN, SH Lee US Patent App. 17/239,892, 2021 | 1 | 2021 |
| On the Modeling of Error Functions as High Dimensional Landscapes for Weight Initialization in Learning Networks Julius, G Mahale, S T, CS Adityakrishna SAMOS 2016, 2016 | 1* | 2016 |
| Apparatus and method with accelerating artificial neural network GV Mahale, PP Udupa, JW Jang, KK Chandrasekharan, SH Lee US Patent App. 18/296,165, 2023 | | 2023 |
| Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress G Mahale, T Limbasiya, MA Aleem, L Plana, A Duricic, A Monemi, ... International Conference on High Performance Computing, 472-485, 2023 | | 2023 |
| Algorithm And Architecture Design for Real-time Face Recognition GV Mahale | | 2017 |
Pramod UdupaIntel LabsVerifierad e-postadress på intel.com
