| VLSI module placement based on rectangle-packing by the sequence-pair H Murata, K Fujiyoshi, S Nakatake, Y Kajitani IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996 | 967 | 1996 |
| Rectangle-packing-based module placement H Murata, K Fujiyoshi, S Nakatake, Y Kajitani The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, 535-548, 2003 | 569 | 2003 |
| Module placement on BSG-structure and IC layout applications S Nakatake, K Fujiyoshi, H Murata, Y Kajitani Proceedings of International Conference on Computer Aided Design, 484-491, 1996 | 404 | 1996 |
| Module packing based on the BSG-structure and IC layout applications S Nakatake, K Fujiyoshi, H Murata, Y Kajitani IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998 | 169 | 1998 |
| VLSI/PCB placement with obstacles based on sequence-pair H Murata, K Fujiyoshi, M Kaneko Proceedings of the 1997 international symposium on Physical design, 26-31, 1997 | 127 | 1997 |
| Arbitrary convex and concave rectilinear block packing using sequence-pair K Fujiyoshi, H Murata Proceedings of the 1999 international symposium on Physical design, 103-110, 1999 | 97 | 1999 |
| A mapping from sequence-pair to rectangular dissection H Murata, K Fujiyoshi, T Watanabe, Y Kajitani Proceedings of ASP-DAC'97: Asia and South Pacific Design Automation …, 1997 | 52 | 1997 |
| Simulated annealing search through general structure floor plans using sequence‐pair K Kiyota, K Fujiyoshi Electronics and Communications in Japan (Part III: Fundamental Electronic …, 2005 | 40 | 2005 |
| Selected sequence-pair: An efficient decodable packing representation in linear time using sequence-pair C Kodama, K Fujiyoshi Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 39 | 2003 |
| Improved method of cell placement with symmetry constraints for analog IC layout design S Kouda, C Kodama, K Fujiyoshi Proceedings of the 2006 international symposium on Physical design, 192-199, 2006 | 27 | 2006 |
| Linear programming-based cell placement with symmetry constraints for analog IC layout S Koda, C Kodama, K Fujiyoshi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 26 | 2007 |
| A tree based novel representation for 3D-block packing K Fujiyoshi, H Kawai, K Ishihara IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 19 | 2009 |
| A novel encoding method into sequence-pair C Kodama, K Fujiyoshi, T Koga 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2004 | 13 | 2004 |
| Method of placing and extracting modules Y Kajitani, K Fujiyoshi, S Nakatake, H Murata US Patent 5,808,898, 1998 | 13 | 1998 |
| Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems Y Kohira, C Kodama, K Fujiyoshi, A Takahashi 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 11 | 2006 |
| DTS: A tree based representation for 3D-block packing K Fujiyoshi, H Kawai, K Ishihara 2007 IEEE International Symposium on Circuits and Systems, 1045-1048, 2007 | 10 | 2007 |
| A fast algorithm for rectilinear block packing based on selected sequence-pair K Fujiyoshi, C Kodama, A Ikeda Integration 40 (3), 274-284, 2007 | 10 | 2007 |
| The O-Sequence: Representation of 3D-floorplan dissected by rectangular walls H Ohta, T Yamada, C Kodama, K Fujiyoshi 2006 Ph. D. Research in Microelectronics and Electronics, 317-320, 2006 | 10 | 2006 |
| IEICE Technical Report H Oka, T Yamamoto, Y Isayama, T Yamamoto MBE88 (19.89) 37, 2004 | 10* | 2004 |
| Design of optimum totally-perfect connection-blocks of FPGA K Fujiyoshi, Y Kajitani, H Niitsu 1994 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 221-224, 1994 | 10 | 1994 |
