Grace Zgheib
Grace Zgheib
Processor Architecture Lab, EPFL
Verifierad e-postadress på epfl.ch
TitelCiteras avÅr
Revisiting and-inverter cones
G Zgheib, L Yang, Z Huang, D Novo, H Parandeh-Afshar, H Yang, ...
Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014
212014
FPRESSO: Enabling express transistor-level exploration of FPGA architectures
G Zgheib, M Lortkipanidze, M Owaida, D Novo, P Ienne
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
132016
Shadow and-inverter cones
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
2013 23rd International Conference on Field programmable Logic and …, 2013
82013
Evaluating FPGA clusters under wide ranges of design parameters
G Zgheib, P Ienne
2017 27th International Conference on Field Programmable Logic and …, 2017
52017
Reducing the pressure on routing resources of FPGAs with generic logic chains
H Parandeh-Afshar, G Zgheib, P Brisk, P Ienne
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
52011
Automatic wire modeling to explore novel FPGA architectures
G Zgheib, P Ienne
2016 International Conference on Field-Programmable Technology (FPT), 181-184, 2016
42016
Improved carry chain mapping for the VTR flow
A Petkovska, G Zgheib, D Novo, M Owaida, A Mishchenko, P Ienne
2015 International Conference on Field Programmable Technology (FPT), 80-87, 2015
42015
Improving circuit mapping performance through mig-based synthesis for carry chains
Z Chu, X Tang, M Soeken, A Petkovska, G Zgheib, L Amarù, Y Xia, ...
Proceedings of the on Great Lakes Symposium on VLSI 2017, 131-136, 2017
32017
Shadow AICs: Reaping the benefits of And-Inverter Cones with minimal architectural impact
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
32013
Routing wire optimization through generic synthesis on FPGA carry chains
H Parandeh-Afshar, G Zgheib, P Brisk, P Ienne
eScholarship, University of California, 2011
32011
A technology mapper for depth-constrained FPGA logic cells
Z Jiang, G Zgheib, CY Lin, D Novo, Z Huang, L Yang, H Yang, P Ienne
2015 25th International Conference on Field Programmable Logic and …, 2015
22015
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element
Z Huang, X Wei, G Zgheib, W Li, Y Lin, Z Jiang, K Tu, P Ienne, H Yang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
12017
Leading the Blind: Automated Transistor-Level Modeling for FPGA Architects
G Zgheib
Ecole Polytechnique Fédérale de Lausanne, 2017
12017
An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components
H Harmanani, D Azar, G Zgheib, D Kozhaya
2015 IEEE International Conference on Information Reuse and Integration, 225-228, 2015
12015
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations
G Zgheib, I Ouaiss
Journal of Circuits, Systems, and Computers 24 (3), 2015
12015
And-inverter cones
G Zgheib, H Parandeh-Afshar, D Novo, P Ienne
Reconfigurable Logic: Architecture, Tools, and Applications, 127-48, 2015
12015
Finding a Needle in the Haystack of Hardened Interconnect Patterns
S Nikolic, G Zgheib, P Ienne
2019 29th International Conference on Field Programmable Logic and …, 2019
2019
Non-LUT field-programmable gate arrays
HP Afshar, DN Bruna, PI Lopez, G Zgheib
US Patent 9,231,594, 2016
2016
Non-LUT field-programmable gate arrays
H Parandeh Afshar, D Novo Bruna, P Ienne Lopez, G Zgheib
2014
Enhanced technology mapping for FPGAs with exploration of cell configurations.(c2011)
GJ Zgheib
2011
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Artiklar 1–20