| A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter K Raczkowski, N Markulic, B Hershberg, J Craninckx Solid-State Circuits, IEEE Journal of 50 (5), 1203 - 1213, 2015 | 147 | 2015 |
| A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS N Markulic, K Raczkowski, P Wambacq, J Craninckx ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 79-82, 2014 | 75 | 2014 |
| A DTC-based subsampling PLL capable of self-calibrated fractional synthesis and two-point modulation N Markulic, K Raczkowski, E Martens, PE Paro Filho, B Hershberg, ... IEEE Journal of Solid-State Circuits 51 (12), 3078-3092, 2016 | 66 | 2016 |
| 24.7 A 673µW 1.8-to-2.5 GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications Y He, YH Liu, T Kuramochi, J van den Heuvel, B Busze, N Markulic, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 420-421, 2017 | 56 | 2017 |
| 3.1 A 3.2 GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion B Hershberg, D Dermit, B van Liempd, E Martens, N Markulic, J Lagos, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 58-60, 2019 | 43 | 2019 |
| A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, ringamp-based pipelined-SAR ADC With background calibration and dynamic reference regulation in 16-nm CMOS J Lagos, N Markulić, B Hershberg, D Dermit, M Shrivas, E Martens, ... IEEE Journal of Solid-State Circuits 57 (4), 1112-1124, 2022 | 32 | 2022 |
| 9.7 a self-calibrated 10mb/s phase modulator with-37.4 db evm based on a 10.1-to-12.4 ghz,-246.6 db-fom, fractional-n subsampling pll N Markulic, K Raczkowski, E Martens, PE Paro Filho, B Hershberg, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 176-177, 2016 | 29 | 2016 |
| A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion B Hershberg, D Dermit, B van Liempd, E Martens, N Markulić, J Lagos, ... IEEE Journal of Solid-State Circuits 56 (8), 2360-2374, 2021 | 25 | 2021 |
| A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm B Hershberg, N Markulić, J Lagos, E Martens, D Dermit, J Craninckx IEEE Journal of Solid-State Circuits 56 (4), 1227-1240, 2021 | 25 | 2021 |
| A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5-GHz bandwidth Q Shi, K Bunsen, N Markulic, J Craninckx IEEE Journal of Solid-State Circuits 54 (12), 3503-3512, 2019 | 25 | 2019 |
| DTC-based PLL and method for operating the DTC-based PLL N Markulic, YH Liu, J Craninckx US Patent 10,200,047, 2019 | 25 | 2019 |
| A 5.5-GHz background-calibrated subsampling polar transmitter with− 41.3-dB EVM at 1024 QAM in 28-nm CMOS N Markulic, PT Renukaswamy, E Martens, B van Liempd, P Wambacq, ... IEEE Journal of Solid-State Circuits 54 (4), 1059-1073, 2019 | 24 | 2019 |
| 3.6 A 6-to-600MS/s fully dynamic ringamp pipelined ADC with asynchronous event-driven clocking in 16nm B Hershberg, B van Liempd, N Markulic, J Lagos, E Martens, D Dermit, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 68-70, 2019 | 23 | 2019 |
| 26.1 A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5 GHz Bandwidth and 100kHz rms Error Q Shi, K Bunsen, N Markulic, J Craninckx 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 408-410, 2019 | 20 | 2019 |
| 17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2 GHz Chirp Bandwidth PT Renukaswamy, N Markulic, S Park, A Kankuppe, Q Shi, P Wambacq, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 278-280, 2020 | 18 | 2020 |
| A 12-mW 10-GHz FMCW PLL based on an integrating DAC with 28-kHz RMS-frequency-error for 23-MHz/μs slope and 1.2-GHz chirp-bandwidth PT Renukaswamy, N Markulic, P Wambacq, J Craninckx IEEE Journal of Solid-State Circuits 55 (12), 3294-3307, 2020 | 17 | 2020 |
| 4.1 A 16GHz, Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL PT Renukaswamy, K Vaesen, N Markulic, V Derudder, DW Park, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 74-76, 2023 | 5 | 2023 |
| Asynchronous event-driven clocking and control in pipelined ADCs B Hershberg, B van Liempd, N Markulić, J Lagos, E Martens, D Dermit, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2813-2826, 2021 | 5 | 2021 |
| An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC L Wei, Z Zheng, N Markulic, J Lagos, E Martens, Y Zhu, CH Chan, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 4 | 2021 |
| Fractional-N sub-sampling PLL using a calibrated delay line for phase noise cancellation PT Renukaswamy, N Markulic, P Wambacq, J Craninckx 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 2 | 2021 |
Jan CraninckxFellow, IMECVerified email at imec.be
