| Noise-resilient SRAM physically unclonable function design for security S Pandey, S Deyati, A Singh, A Chatterjee 2016 IEEE 25th Asian Test Symposium (ATS), 55-60, 2016 | 26 | 2016 |
| An automated design methodology for yield aware analog circuit synthesis in submicron technology S Deyati, P Mandal 2011 12th International Symposium on Quality Electronic Design, 1-7, 2011 | 18 | 2011 |
| Targeting hardware Trojans in mixed-signal circuits for security S Deyati, BJ Muldrey, A Chatterjee 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 1-4, 2016 | 15 | 2016 |
| Adaptive testing of analog/RF circuits using hardware extracted FSM models S Deyati, BJ Muldrey, A Chatterjee 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 14 | 2016 |
| A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time B Querbach, R Khanna, D Blankenbeckler, Y Zhang, RT Anderson, ... 2014 International Test Conference, 1-10, 2014 | 14 | 2014 |
| Analog push pull amplifier-based physically unclonable function for hardware security S Deyati, A Chatterjee, BJ Muldrey US Patent 10,211,993, 2019 | 13 | 2019 |
| Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits S Deyati, BJ Muldrey, A Banerjee, A Chatterjee 2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014 | 13 | 2014 |
| High resolution pulse propagation driven Trojan detection in digital logic: optimization algorithms and infrastructure S Deyati, BJ Muldrey, A Singh, A Chatterjee 2014 IEEE 23rd Asian Test Symposium, 200-205, 2014 | 11 | 2014 |
| Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits A Chatterjee, S Deyati, B Muldrey, S Devarakond, A Banerjee Proceedings of the International Conference on Computer-Aided Design, 553-556, 2012 | 11 | 2012 |
| Challenge engineering and design of analog push pull amplifier based physically unclonable function for hardware security S Deyati, BJ Muldrey, AD Singh, A Chatterjee 2015 IEEE 24th Asian test symposium (ATS), 127-132, 2015 | 10 | 2015 |
| RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning B Muldrey, S Deyati, M Giardino, A Chatterjee 2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013 | 10 | 2013 |
| Vast: Post-silicon validation and diagnosis of rf/mixed-signal circuits using signature tests S Deyati, A Banerjee, BJ Muldrey, A Chatterjee 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 10 | 2013 |
| Design of efficient analog physically unclonable functions using alternative test principles S Deyati, B Muldrey, A Singh, A Chatterjee 2017 International Mixed Signals Testing Workshop (IMSTW), 1-4, 2017 | 9 | 2017 |
| Concurrent built in test and tuning of beamforming mimo systems using learning assisted performance optimization S Deyati, BJ Muldrey, B Jung, A Chatterjee 2017 IEEE International Test Conference (ITC), 1-10, 2017 | 7 | 2017 |
| BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking S Deyati, B Muldrey, A Chatterjee Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 5 | 2017 |
| Trojan detection in digital systems using current sensing of pulse propagation in logic gates S Deyati, BJ Muldrey, A Chatterjee 2016 17th International Symposium on Quality Electronic Design (ISQED), 350-355, 2016 | 5 | 2016 |
| TRAP: Test generation driven classification of analog/RF ICs using adaptive probabilistic clustering algorithm S Deyati, BJ Muldrey, A Chatterjee 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 5 | 2016 |
| Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. S Deyati Georgia Institute of Technology, Atlanta, GA, USA, 2017 | 4 | 2017 |
| Concurrent stimulus and defect magnitude optimization for detection of weakest shorts and opens in analog circuits B Muldrey, S Deyati, A Chatterjee 2016 IEEE 25th Asian Test Symposium (ATS), 96-101, 2016 | 3 | 2016 |
| Low cost signal reconstruction based testing of RF components using incoherent undersampling D Bhatta, A Banerjee, S Deyati, N Tzou, A Chatterjee Journal of Electronic Testing 30, 213-228, 2014 | 3 | 2014 |
Barry MuldreyIntel CorporationVerifierad e-postadress på muldrey.net
