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Hung-Ming Chen
Hung-Ming Chen
Verifierad e-postadress på g2.nctu.edu.tw - Startsida
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Integrated floorplanning and interconnect planning
HM Chen, MDF Wong, H Zhou, FY Young, HH Yang, N Sherwani
Layout optimization in VLSI design, 1-18, 2001
1062001
Fast analog layout prototyping for nanometer design migration
YP Weng, HM Chen, TC Chen, PC Pan, CH Chen, WZ Chen
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 517-522, 2011
432011
On optimizing scan testing power and routing cost in scan chain design
LC Hsu, HM Chen
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-456, 2006
332006
Floorplanning with power supply noise avoidance
HM Chen, LD Huang, IM Liu, M Lai, DF Wong
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
332003
Simultaneous power supply planning and noise avoidance in floorplan design
HM Chen, LD Huang, IM Liu, MDF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
322005
Esd protection structure for 3d ic
KN Chen, MF Lai, HM Chen
US Patent App. 13/041,358, 2012
292012
Closing the gap between global and detailed placement: Techniques for improving routability
CK Wang, CC Huang, SSY Liu, CY Chin, ST Hu, WC Wu, HM Chen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
282015
Integrated power supply planning and floorplanning
IM Liu, HM Chen, TL Chou, A Aziz, DF Wong
Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001
282001
Configurable analog routing methodology via technology and design constraint unification
PC Pan, HM Chen, YK Cheng, J Liu, WY Hu
Proceedings of the International Conference on Computer-Aided Design, 620-626, 2012
272012
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping
KH Meng, PC Pan, HM Chen
2011 12th International Symposium on Quality Electronic Design, 1-8, 2011
262011
A fast prototyping framework for analog layout migration with planar preservation
PC Pan, CY Chin, HM Chen, TC Chen, CC Lee, JC Lin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
222015
Analog placement with current flow and symmetry constraints using PCP-SP
A Patyal, PC Pan, HM Chen, HY Chi, CN Liu
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
212018
Fast flip-chip pin-out designation respin for package-board codesign
RJ Lee, HM Chen
IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009
212009
Flexible droplet routing in active matrix–based digital microfluidic biochips
GR Lu, CH Kuo, KC Chiang, A Banerjee, BB Bhattacharya, TY Ho, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (3 …, 2018
202018
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
SSY Liu, WT Lo, CJ Lee, HM Chen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (3 …, 2013
192013
On construction low power and robust clock tree via slew budgeting
YC Chang, CK Wang, HM Chen
Proceedings of the 2012 ACM international symposium on International …, 2012
192012
On routing fixed escaped boundary pins for high speed boards
TY Tsai, RJ Lee, CY Chin, CY Kuan, HM Chen, Y Kajitani
2011 Design, Automation & Test in Europe, 1-6, 2011
182011
I/O clustering in design cost and performance optimization for flip-chip design
HM Chen, IM Liu, MDF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
182006
ACER: An agglomerative clustering based electrode addressing and routing algorithm for pin-constrained EWOD chips
SSY Liu, CH Chang, HM Chen, TY Ho
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
172014
Effective power network prototyping via statistical-based clustering and sequential linear programming
SSY Liu, CJ Lee, CC Huang, HM Chen, CT Lin, CH Lee
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
172013
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Artiklar 1–20