Vojin G. Oklobdzija
Vojin G. Oklobdzija
University of California, Emeritus Professor, IEEE Life Fellow, President IEEE CAS
Verifierad e-postadress på ieee.org - Startsida
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New generation of predictive technology model for sub-45 nm early design exploration
W Zhao, Y Cao
IEEE Transactions on Electron Devices 53 (11), 2816-2823, 2006
13182006
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
V Stojanovic, VG Oklobdzija
IEEE Journal of solid-state circuits 34 (4), 536-548, 1999
7941999
Improved sense-amplifier-based flip-flop: Design and measurements
B Nikolic, VG Oklobdzija, V Stojanovic, W Jia, JKS Chiu, MMT Leung
IEEE Journal of Solid-State Circuits 35 (6), 876-884, 2000
5082000
A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
VG Oklobdzija, D Villeger, SS Liu
IEEE Transactions on computers 45 (3), 294-306, 1996
4271996
Pass-transistor adiabatic logic using single power-clock supply
VG Oklobdzija, D Maksimovic, F Lin
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997
2571997
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
D Maksimovic, VG Oklobdzija, B Nikolic, KW Current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 460-463, 2000
2272000
Digital system clocking: high-performance and low-power aspects
VG Oklobdzija, VM Stojanovic, DM Markovic, NM Nedovic
John Wiley & Sons, 2005
2182005
Digital system clocking: high-performance and low-power aspects
VG Oklobdzija, VM Stojanovic, DM Markovic, NM Nedovic
John Wiley & Sons, 2005
2182005
Digital system clocking: high-performance and low-power aspects
VG Oklobdzija, VM Stojanovic, DM Markovic, NM Nedovic
John Wiley & Sons, 2005
2182005
An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis
VG Oklobdzija
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (1), 124-128, 1994
2101994
Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
J Cocke, GF Grohoski, VG Oklobdzija
US Patent 4,992,938, 1991
1821991
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
VG Oklobdzija, D Villeger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (2), 292-301, 1995
1701995
Optimal circuits for parallel multipliers
PF Stelling, CU Martel, VG Oklobdzija, R Ravi
IEEE Transactions on Computers 47 (3), 273-285, 1998
1681998
Comparison of high-performance VLSI adders in the energy-delay space
VG Oklobdzija, BR Zeydel, HQ Dao, S Mathew, R Krishnamurthy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 754-758, 2005
1242005
Instruction prefetch buffer control
VG Oklobdzija, DT Ling
US Patent 4,714,994, 1987
1211987
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS
SK Hsu, SK Mathew, MA Anders, BR Zeydel, VG Oklobdzija, ...
IEEE Journal of solid-state circuits 41 (1), 256-264, 2005
1122005
Conditional pre-charge techniques for power-efficient dual-edge clocking
N Nedovic, M Aleksic, VG Oklobdzija
Proceedings of the International Symposium on Low Power Electronics and …, 2002
1122002
Integrated power clock generators for low energy logic
D Maksimovic, VG Oklobdzija
Proceedings of PESC'95-Power Electronics Specialist Conference 1, 61-67, 1995
1051995
Clocking and clocked storage elements in a multi-gigahertz environment
VG Oklobdzija
IBM Journal of Research and Development 47 (5.6), 567-583, 2003
1032003
Dual-edge triggered storage elements and clocking strategy for low-power systems
N Nedovic, VG Oklobdzija
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (5), 577-590, 2005
982005
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Artiklar 1–20