| A 6.7-GHz active gate driver for GaN FETs to combat overshoot, ringing, and EMI HCP Dymond, J Wang, D Liu, JJO Dalton, N McNeill, D Pamunuwa, ... IEEE Transactions on Power Electronics 33 (1), 581-594, 2017 | 196 | 2017 |
| Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs R Weerasekera, LR Zheng, D Pamunuwa, H Tenhunen 2007 IEEE/ACM International Conference on Computer-Aided Design, 212-219, 2007 | 135 | 2007 |
| Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits R Weerasekera, M Grange, D Pamunuwa, H Tenhunen, LR Zheng 2009 IEEE International Conference on 3D System Integration, 1-8, 2009 | 130 | 2009 |
| Maximizing throughput over parallel wire structures in the deep submicrometer regime D Pamunuwa, LR Zheng, H Tenhunen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (2), 224-243, 2003 | 102 | 2003 |
| Scalability of network-on-chip communication architecture for 3-D meshes AY Weldezion, M Grange, D Pamunuwa, Z Lu, A Jantsch, R Weerasekera, ... 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 114-123, 2009 | 78 | 2009 |
| Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints R Weerasekera, D Pamunuwa, LR Zheng, H Tenhunen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 57 | 2009 |
| Repeater insertion to minimise delay in coupled interconnects D Pamunuwa, H Tenhunen VLSI Design 2001. Fourteenth International Conference on VLSI Design, 513-517, 2001 | 45 | 2001 |
| On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits R Weerasekera, M Grange, D Pamunuwa, H Tenhunen 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 42 | 2010 |
| Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory S Rana, J Mouro, SJ Bleiker, R Jamie D., HMH Chong, F Niklaus, ... Nature Communications 11, 1181, 2020 | 41 | 2020 |
| Nano-crystalline graphite for reliability improvement in MEM relay contacts S Rana, JD Reynolds, TY Ling, MS Shamsudin, SH Pu, HMH Chong, ... Carbon 133, 193-199, 2018 | 37 | 2018 |
| Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen VLSI-SOC, 362-, 2003 | 32 | 2003 |
| Full custom design of an arbitrary waveform gate driver with 10-GHz waypoint rates for GaN FETs D Liu, HCP Dymond, SJ Hollis, J Wang, N McNeill, D Pamunuwa, ... IEEE Transactions on Power Electronics 36 (7), 8267-8279, 2020 | 30 | 2020 |
| Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays T Qin, SJ Bleiker, S Rana, F Niklaus, D Pamunuwa IEEE Access, 2018 | 28 | 2018 |
| Shaping switching waveforms in a 650 V GaN FET bridge-leg using 6.7 GHz active gate drivers JJO Dalton, J Wang, HCP Dymond, D Liu, D Pamunuwa, BH Stark, ... 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), 1983-1989, 2017 | 23 | 2017 |
| Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-resistance patterns HCP Dymond, D Liu, J Wang, JJO Dalton, N McNeill, D Pamunuwa, ... 2016 IEEE Energy Conversion Congress and Exposition (ECCE), 1-6, 2016 | 23 | 2016 |
| Energy and latency optimization in NEM relay-based digital circuits S Rana, T Qin, A Bazigos, D Grogg, M Despont, CL Ayala, C Hagleitner, ... IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2348-2359, 2014 | 23 | 2014 |
| Wire-bonded through-silicon vias with low capacitive substrate coupling AC Fischer, M Grange, N Roxhed, R Weerasekera, D Pamunuwa, ... Journal of Micromechanics and Microengineering 21 (8), 085035, 2011 | 23 | 2011 |
| Analytical compact model in Verilog-A for electrostatically actuated ohmic switches A Bazigos, CL Ayala, M Fernandez-Bolanos, Y Pu, D Grogg, C Hagleitner, ... IEEE Transactions on Electron Devices 61 (6), 2186-2194, 2014 | 21 | 2014 |
| Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design LR Zheng, D Pamunuwa, H Tenhunen Proceedings of the 26th European Solid-State Circuits Conference, 352-355, 2000 | 21 | 2000 |
| A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen Integration 38 (1), 3-17, 2004 | 20 | 2004 |
Roshan WeerasekaraSenior Lecturer in MicroelectronicsVerified email at bristol.ac.uk
