| Semiconductor device KK Bhuwalka, SJ Kim, JC Kim, H Kim US Patent 10,217,816, 2019 | 61 | 2019 |
| Universality of short-channel effects on ultrascaled MOSFET performance MA Pourghaderi, AT Pham, H Ilatikhameneh, J Kim, HH Park, S Jin, ... IEEE Electron Device Letters 39 (2), 168-171, 2017 | 18 | 2017 |
| Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays N Xu, J Wang, Y Deng, Y Lu, B Fu, W Choi, U Monga, J Jeon, J Kim, ... 2016 IEEE International Electron Devices Meeting (IEDM), 7.7. 1-7.7. 4, 2016 | 18 | 2016 |
| Comprehensive simulation study of direct source-to-drain tunneling in ultra-scaled Si, Ge, and III-V DG-FETs Z Jiang, J Wang, HH Park, AT Pham, N Xu, Y Lu, S Jin, W Choi, ... IEEE Transactions on Electron Devices 64 (3), 945-952, 2017 | 13 | 2017 |
| Layout-induced stress effects on the performance and variation of FinFETs C Lee, HC Kang, JG Min, J Kim, U Kwon, KH Lee, Y Park 2015 International Conference on Simulation of Semiconductor Processes and …, 2015 | 7 | 2015 |
| Performance evaluation of FinFETs: from multisubband BTE to DD calibration S Jin, AT Pham, W Choi, MA Pourghaderi, J Kim, KH Lee 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 6 | 2016 |
| Semiconductor device SH Song, YS Kim, KB Chang, UH Kwon, YH Kim, JC Kim, CW Jeong US Patent 10,504,894, 2019 | 5 | 2019 |
| Band-to-band tunneling in SiGe: Influence of alloy scattering S Jin, HH Park, M Luisier, W Choi, J Kim, KH Lee IEEE Electron Device Letters 38 (4), 422-425, 2017 | 5 | 2017 |
| Circuit design method and simulation method based on process variation caused by aging JW Jeon, JH Choi, YH Kim, KH Lee, U Kwon, JC Kim US Patent App. 15/251,411, 2017 | 4 | 2017 |
| Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications S Dhar, HK Noh, SJ Kim, HW Kim, Z Wu, WS Lee, KK Bhuwalka, JC Kim, ... 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 4 | 2016 |
| An effective algorithm for numerical Schrödinger solver of quantum well structures J Kim, CY Chen, RW Dutton Journal of Computational Electronics 7, 1-5, 2008 | 3 | 2008 |
| Circuit design method and simulation method based on random telegraph signal noise JW Jeon, HE Park, KH Lee, U Kwon, JC Kim US Patent 10,311,187, 2019 | 2 | 2019 |
| Nanoscale-nMOSFET junction design: Quantum transport approach MA Pourghaderi, C Park, J Kim, C Jeong, WY Chung, KH Lee, HH Park, ... 2017 International Conference on Simulation of Semiconductor Processes and …, 2017 | 2 | 2017 |
| On the efficient methods to solve multi-subband BTE in 1D gas systems: Decoupling approximations versus the accurate approach AT Pham, Z Jiang, S Jin, J Wang, W Choi, MA Pourghaderi, J Kim, KH Lee 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 2 | 2016 |
| A new weight redistribution technique for electron-electron scattering in the MC simulation J Kim, H Shin, C Lee, YJ Park, HS Min IEEE transactions on electron devices 51 (9), 1448-1454, 2004 | 2 | 2004 |
| Atomistic simulation of band-to-band tunneling in SiGe: Influence of alloy scattering HH Park, S Jin, W Choi, M Luisier, J Kim, KH Lee 2017 International Conference on Simulation of Semiconductor Processes and …, 2017 | 1 | 2017 |
| Semiconductor device and method of fabricating the same S Son, D Bae, J Kim, SC Paek US Patent App. 12/955,084, 2011 | 1 | 2011 |
| Lateral Ge/SiGe/Si hetero-channel p-type MOSFETs CY Chen, Y Liu, J Kim, RW Dutton 2009 International Conference on Simulation of Semiconductor Processes and …, 2009 | | 2009 |
| A Simple Technique for the Monte Carlo Simulation of Transport in Quantum Wells J Kim, CY Chen, RW Dutton Simulation of Semiconductor Processes and Devices 2007: SISPAD 2007, 77-80, 2007 | | 2007 |
| Nonlocal transport and thermal noise of the nanoscale MOSFET YJ Park, S Jin, S Hong, HS Min Noise in Devices and Circuits II 5470, 74-83, 2004 | | 2004 |
