| 15.3 a 65nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement, adaptive analog sparsity and 44TOPS/W system energy efficiency Z Chen, X Chen, J Gu 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 240-242, 2021 | 71 | 2021 |
| On the tool manipulation capability of open-source large language models Q Xu, F Hong, B Li, C Hu, Z Chen, J Zhang arXiv preprint arXiv:2305.16504, 2023 | 41 | 2023 |
| High-throughput dynamic time warping accelerator for time-series classification with pipelined mixed-signal time-domain computing Z Chen, J Gu IEEE Journal of Solid-State Circuits 56 (2), 624-635, 2020 | 20 | 2020 |
| A time-domain computing accelerated image recognition processor with efficient time encoding and non-linear logic operation Z Chen, J Gu IEEE Journal of Solid-State Circuits 54 (11), 3226-3237, 2018 | 18 | 2018 |
| A mixed-signal time-domain generative adversarial network accelerator with efficient subthreshold time multiplier and mixed-signal on-chip training for low power edge devices Z Chen, S Fu, Q Cao, J Gu 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 14 | 2020 |
| Analysis and design of energy efficient time domain signal processing Z Chen, J Gu Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 12 | 2016 |
| True random number generator in 0.35/μm for RFID applications Z Chen, W Yin, K Boyle 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 9 | 2015 |
| Digital compatible synthesis, placement and implementation of mixed-signal time-domain computing Z Chen, H Zhou, J Gu Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 7 | 2019 |
| 19.7 A scalable pipelined time-domain DTW engine for time-series classification using multibit time flip-flops with 140Giga-cell-updates/s throughput Z Chen, J Gu 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 324-326, 2019 | 7 | 2019 |
| R-accelerator: An RRAM-based CGRA accelerator with logic contraction Z Chen, H Zhou, J Gu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019 | 6 | 2019 |
| A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. Z Chen, J Gu ISSCC, 324-326, 2019 | 5 | 2019 |
| An image recognition processor with time-domain accelerators using efficient time encoding and non-linear logic operation Z Chen, J Gu 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 257-260, 2018 | 5 | 2018 |
| A comprehensive stochastic design methodology for hold-timing resiliency in voltage-scalable design Z Chen, H Wang, G Xie, J Gu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018 | 5 | 2018 |
| Classification of leaf shapes and estimation of leaf mass Y Hong, Z Chen, J Qiu 2012 International Conference on Green and Ubiquitous Technology, 167-171, 2012 | 3 | 2012 |
| R-accelerator: A reconfigurable accelerator with RRAM based logic contraction and resource optimization for application specific computing Z Chen, H Zhou, J Gu 2018 IEEE 36th International Conference on Computer Design (ICCD), 163-170, 2018 | 2 | 2018 |
| A rram-based coarse grain reconfigurable array for neural network accelerators Z Chen, H Zhou, J Gu 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 1 | 2018 |
| Computing-in-memory accelerator design with dynamic analog RAM cell and associated low power techniques with sparsity management J Gu, Z Chen US Patent 11,955,167, 2024 | | 2024 |
| Exploring the Use of Dataflow Architectures for Graph Neural Network Workloads R Hosseini, F Simini, V Vishwanath, R Sivakumar, S Shanmugavelu, ... International Conference on High Performance Computing, 648-661, 2023 | | 2023 |
| AI SoC Design Challenges in the Foundation Model Era Z Chen, D Huang, M Wang, B Yang, JL Shin, C Hu, B Li, R Prabhakar, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2023 | | 2023 |
| System and method for pipelined time-domain computing using time-domain flip-flops and its application in time-series analysis J Gu, Z Chen US Patent 11,467,831, 2022 | | 2022 |
Jie GuProfessor of Electrical Engineering and Computer Science, Northwestern UniversityVerifierad e-postadress på northwestern.edu
