On-chip interconnection architecture of the tile processor D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ... IEEE micro 27 (5), 15-31, 2007 | 1012 | 2007 |
Tile64-processor: A 64-core soc with mesh interconnect S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 760 | 2008 |
Computing in parallel processing environments PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ... US Patent 8,738,860, 2014 | 214 | 2014 |
Configuring routing in mesh networks L Bao, IR Bratt US Patent 8,050,256, 2011 | 103 | 2011 |
Buffering system bus for external-memory access L Bao US Patent 6,708,257, 2004 | 94 | 2004 |
Tile processor: Embedded multicore for networking and multimedia A Agarwal, L Bao, J Brown, B Edwards, M Mattina, CC Miao, C Ramey, ... Hot Chips 19, 2007 | 78 | 2007 |
Spinal fusion using an HMG-CoA reductase inhibitor BJ Remington, DJ Bearss, K Shahi US Patent 7,041,309, 2006 | 36 | 2006 |
Configuring routing in mesh networks L Bao, IR Bratt US Patent 8,045,546, 2011 | 26 | 2011 |
Memory controller with prefetching capability SC Woo, BA May, L Bao US Patent 7,370,152, 2008 | 17 | 2008 |
Memory controller load balancing with configurable striping domains L Bao US Patent 9,063,825, 2015 | 14 | 2015 |
Managing memory requests based on priority L Bao US Patent 8,886,899, 2014 | 12 | 2014 |
Configuring routing in mesh networks L Bao, IR Bratt US Patent 8,151,088, 2012 | 9 | 2012 |
Configuring routing in mesh networks L Bao, IR Bratt US Patent 8,737,392, 2014 | 6 | 2014 |
Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design L Bao, TA Pontius US Patent 6,543,030, 2003 | 5 | 2003 |
Memory control system with incrementer for generating speculative addresses L Bao US Patent 6,701,422, 2004 | 4 | 2004 |
Configuring routing in mesh networks L Bao, IR Bratt US Patent 9,384,165, 2016 | 3 | 2016 |
Memory controller load balancing with configurable striping domains L Bao US Patent 9,753,854, 2017 | 2 | 2017 |
Networks of the Tilera Multicore Processor1 D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ... Designing Network On-Chip Architectures in the Nanoscale Era, 275-300, 2010 | | 2010 |
ISSCC 2008/SESSION 4/MICROPROCESSORS/4.4 S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ... | | |