Cheng-Chieh Huang
Cheng-Chieh Huang
Verified email at google.com - Homepage
Title
Cited by
Cited by
Year
ATCache: reducing DRAM cache latency via a small SRAM tag cache
CC Huang, V Nagarajan
Proceedings of the 23rd international conference on Parallel architectures …, 2014
862014
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
212016
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches
CC Huang, R Kumar, M Elver, B Grot, V Nagarajan
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
122016
Boomerang: A metadata-free architecture for control flow delivery
R Kumar, CC Huang, B Grot, V Nagarajan
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
92017
DCA: a DRAM-cache-aware DRAM controller
CC Huang, V Nagarajan, A Joshi
SC'16: Proceedings of the International Conference for High Performance …, 2016
62016
Increasing cache capacity via critical-words-only cache
CC Huang, V Nagarajan
2014 IEEE 32nd International Conference on Computer Design (ICCD), 125-132, 2014
62014
Branch target buffer for a data processing apparatus
R Kumar, B Grot, V Nagarajan, CC Huang
2018
Optimizing cache utilization in modern cache hierarchies
CC Huang
The University of Edinburgh, 2016
2016
The system can't perform the operation now. Try again later.
Articles 1–8