| Performance evaluation of single-and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks AMP Amorim, PAC Oliveira, HC Freitas Journal of the Brazilian Computer Society 21, 1-16, 2015 | 7 | 2015 |
| DNAr-Logic: A constructive DNA logic circuit design library in R language for Molecular Computing RA Marks, DKS Vieira, MV Guterres, PAC Oliveira, OPV Neto Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 12, 2019 | 6 | 2019 |
| A greedy heuristic for process mapping on networks-on-chip PAC Oliveira, CP Avelar, SJF Guimaraes, HC Freitas Anais do XII Simpósio em Sistemas Computacionais de Alto Desempenho, 25-32, 2011 | 6 | 2011 |
| Evaluating analog arithmetic circuit for approximate computing with DNA strand displacement PAC Oliveira, JVC Teixeira, RA Marks, MV Guterres, OPV Neto Analog Integrated Circuits and Signal Processing 108 (3), 485-493, 2021 | 5 | 2021 |
| DNAr: An R package to simulate and analyze CRN and DSD networks DKS Vieira, MV Guterres, RA Marks, PAC Oliveira, MCO Fonte Boa, ... ACS Synthetic Biology 9 (12), 3416-3421, 2020 | 5 | 2020 |
| Analysis of single-module and cascade molecular analog circuits for approximate computing based on DNA Strand Displacement PAC Oliveira, MCOF Boa, RA Marks, MV Guterres, OPV Neto 33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020), 2020 | 4 | 2020 |
| Integrando traços de execução de aplicações paralelas ao network simulator para simulação de winoc AMP Amorim, PAC Oliveira, HC Freitas Anais.. WSCAD-WIC, Petrópolis, 1-4, 2012 | 4 | 2012 |
| Avaliação de desempenho e caracterização de cargas de trabalho paralelas para redes-em-chip sem fio PAC Oliveira Mestrado, Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, 2012 | 4 | 2012 |
| Performance evaluation of winocs for parallel workloads based on collective communications PAC Oliveira, FLP Duarte-Figueiredo, C Martins, HC Freitas, CP Ribeiro, ... Proc. IADIS Applied Computing. IADIS Applied Computing, Rio de Janeiro, 307-314, 2011 | 4 | 2011 |
| Evaluating the problem of process mapping on network-on-chip for parallel applications CP Avelar, PAC Oliveira, HC Freitas, POA Navaux 2011 Second Workshop on Architecture and Multi-Core Applications (wamca 2011 …, 2011 | 3 | 2011 |
| DNAr-Analog: A Library With a Multiplexer to Easily Design, Program, and Simulate Dsd Analog Circuits PAC Oliveira, RA Marks, JVC Teixeira, MV Guterres, OPV Neto 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), 1-4, 2023 | 1 | 2023 |
| Design Automation for Emerging Technologies O Paranaiba, P Oliveira, R Marks, G Novy, M Vieira, LO Luz, PA Silva, ... Journal of Integrated Circuits and Systems 17 (3), 1-11, 2022 | 1 | 2022 |
| Design and Test of Digital Logic DNA Systems RA Marks, DKS Vieira, MV Guterres, PAC Oliveira, MCOF Boa, OPV Neto IEEE Design & Test 38 (4), 94-101, 2021 | 1 | 2021 |
| Design Automation for Emerging Technologies PAC Oliveira, RA Marks, GFC Novy, MD Vieira, LO Luz, PARL Silva, ... Journal of Integrated Circuits and Systems 17 (3), 1, 2022 | | 2022 |
| Avaliação do desempenho do uso de Sistemas Gerenciadores de Bancos de Dados Orientados a Objetos para armazenamento de dados multimídia BEP Marques, IMR Machado, PAC de Oliveira Anais Estendidos do XVI Simpósio Brasileiro de Sistemas Multimídia e Web, 59-62, 2010 | | 2010 |
