From software to accelerators with LegUp high-level synthesis A Canis, J Choi, B Fort, R Lian, Q Huang, N Calagar, M Gort, JJ Qin, ... 2013 International Conference on Compilers, Architecture and Synthesis for …, 2013 | 81 | 2013 |
The effect of compiler optimizations on high-level synthesis for FPGAs Q Huang, R Lian, A Canis, J Choi, R Xi, S Brown, J Anderson 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013 | 76 | 2013 |
FPGA-based CNN inference accelerator synthesized from multi-threaded C software JH Kim, B Grady, R Lian, J Brothers, JH Anderson 2017 30th IEEE International System-on-Chip Conference (SOCC), 268-273, 2017 | 56 | 2017 |
The effect of compiler optimizations on high-level synthesis-generated hardware Q Huang, R Lian, A Canis, J Choi, R Xi, N Calagar, S Brown, J Anderson ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (3), 1-26, 2015 | 54 | 2015 |
Automating the design of processor/accelerator embedded systems with legup high-level synthesis B Fort, A Canis, J Choi, N Calagar, R Lian, S Hadjis, YT Chen, M Hall, ... 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing …, 2014 | 46 | 2014 |
Legup high-level synthesis A Canis, J Choi, B Fort, B Syrowik, RL Lian, YT Chen, H Hsiao, J Goeders, ... FPGAs for Software Programmers, 175-190, 2016 | 30 | 2016 |
Accelerating memcached on aws cloud fpgas J Choi, R Lian, Z Li, A Canis, J Anderson Proceedings of the 9th International Symposium on Highly-Efficient …, 2018 | 15 | 2018 |
A framework for FPGA-based acceleration of neural network inference with limited numerical precision via high-level synthesis with streaming functionality RL Lian University of Toronto (Canada), 2016 | 13 | 2016 |
From C to Blokus Duo with LegUp high-level synthesis JC Cai, R Lian, M Wang, A Canis, J Choi, B Fort, E Hart, E Miao, Y Zhang, ... 2013 International Conference on Field-Programmable Technology (FPT), 486-489, 2013 | 8 | 2013 |
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware J Choi, RL Lian, S Brown, J Anderson 2016 IEEE 27th International Conference on Application-specific Systems …, 2016 | 7 | 2016 |
High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware J Choi, R Lian, AC Canis, JH Anderson US Patent 10,579,762, 2020 | 6 | 2020 |
High-Level-Synthesis for RISC-V System-on-Chip Generation for Field Programmable Gate Arrays J Choi, D Ma, R Lian US Patent App. 18/208,381, 2023 | | 2023 |
High-level synthesis (HLS) method and apparatus to specify parallelism in computer hardware J Choi, R Lian, AC Canis, JH Anderson, MR Soliman US Patent 11,816,406, 2023 | | 2023 |
High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware J Choi, R Lian, AC Canis, JH Anderson US Patent 11,055,456, 2021 | | 2021 |
Additional Reviewers FCCM 2014 A Agne, R Ahmed, J Ambrose, J Anwer, S Bayliss, T Becker, ... | | |