| 340mV-1.1 V, 289Gbps/W, 2090-gate NanoAES Hardware Accelerator with Area-optimized Encrypt/Decrypt GF (2 4) 2 Polynomials in 22nm tri-gate CMOS S Mathew, S Satpathy, V Suresh, H Kaul, M Anders, G Chen, A Agarwal, ... IEEE Symposium on VLSI Circuits, 2014 | 94 | 2014 |
| Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance VB Suresh, SK Mathew, SK Satpathy US Patent App. 10/027,472, 2018 | 49* | 2018 |
| Hybrid SM3 and SHA acceleration processors SK Satpathy, VB Suresh, SK Mathew US Patent App. 10/129,018, 2018 | 35* | 2018 |
| Entropy extraction in metastability-based TRNG VB Suresh, WP Burleson Hardware-Oriented Security and Trust (HOST), 2010 IEEE International …, 2010 | 31 | 2010 |
| µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ... J. Solid-State Circuits 51 (7), 1695-1704, 2016 | 29 | 2016 |
| A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ... IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017 | 25 | 2017 |
| Energy-efficient dual-rail keeperless domino datapath circuits VB Suresh, SK Mathew, SK Satpathy US Patent App. 10/164,773, 2018 | 22* | 2018 |
| On-chip lightweight implementation of reduced NIST randomness test suite VB Suresh, D Antonioli, WP Burleson 2013 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2013 | 22 | 2013 |
| Implementing hardware trojans: Experiences from a hardware trojan challenge GT Becker, A Lakshminarasimhan, L Lin, S Srivathsa, VB Suresh, ... 2011 IEEE 29th International Conference on Computer Design (ICCD), 301-304, 2011 | 21 | 2011 |
| Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing VB Suresh, WP Burleson IEEE Transactions on Circuits and Systems I: Regular Papers 62 (7), 1785-1793, 2015 | 18 | 2015 |
| Memory access control system and method R Schreiber, V Suresh US Patent US 9013949 B2, 2013 | 12 | 2013 |
| Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration VB Suresh, WP Burleson Thirteenth International Symposium on Quality Electronic Design (ISQED), 298-305, 2012 | 11 | 2012 |
| Hybrid AES-SMS4 hardware accelerator V Suresh, S Satpathy, S Mathew US Patent App. 10/218,497, 2019 | 10* | 2019 |
| Ultra-low energy security circuits for IoT applications S Satpathy, S Mathew, V Suresh, R Krishnamurthy 2016 IEEE 34th International Conference on Computer Design (ICCD), 682-685, 2016 | 10 | 2016 |
| μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS S Mathew, D Johnston, P Newman, S Satpathy, V Suresh, M Anders, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 10 | 2015 |
| Lithography aware critical area estimation and yield analysis P Vijayakumar, VB Suresh, S Kundu 2011 IEEE International Test Conference, 1-8, 2011 | 10 | 2011 |
| Post-silicon validation and calibration of hardware security primitives X Xu, V Suresh, R Kumar, W Burleson 2014 IEEE Computer Society Annual Symposium on VLSI, 29-34, 2014 | 9 | 2014 |
| On-chip True Random Number Generation in Nanometer CMOS VB Suresh | 8 | 2012 |
| 2.9 TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS M Anders, H Kaul, S Mathew, V Suresh, S Satpathy, A Agarwal, S Hsu, ... 2018 IEEE Symposium on VLSI Circuits, 39-40, 2018 | 7 | 2018 |
| Compact, low power advanced encryption standard circuit S Mathew, V Suresh, S Satpathy, M Anders, H Kaul, R Krishnamurthy US Patent 9,843,441, 2017 | 7 | 2017 |
Sudhir SatpathyCompute Silicon Architect, Facebook Reality LabsVerifierad e-postadress på fb.com
