| Analog placement with current flow and symmetry constraints using PCP-SP A Patyal, PC Pan, HM Chen, HY Chi, CN Liu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 21 | 2018 |
| Pole-aware analog layout synthesis considering monotonic current flows and wire crossings A Patyal, HM Chen, MPH Lin, GQ Fang, SYH Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 6 | 2022 |
| Achieving analog layout integrity through learning and migration MPH Lin, HY Chi, A Patyal, ZY Liu, JJ Zhao, CNJ Liu, HM Chen Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 6 | 2020 |
| Exploring multiple analog placements with partial-monotonic current paths and symmetry constraints using PCP-SP A Patyal, PC Pan, KA Asha, HM Chen, WZ Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 4 | 2020 |
| Improving the quality of FPGA RO-PUF by principal component analysis (PCA) KA Asha, LE Hsu, A Patyal, HM Chen ACM Journal on Emerging Technologies in Computing Systems 17 (3), 3442444, 2021 | 3 | 2021 |
| Late breaking results: Pole-aware analog placement considering monotonic current flow and crossing-wire minimization A Patyal, HM Chen, MPH Lin 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-2, 2020 | 2 | 2020 |
| Method for layout generation with constrained hypergraph partitioning Y Tsun-Yu, WY Hu, JF Kuan, HS Lee, PC Pan, HW Huang, HM Chen, ... US Patent 10,509,883, 2019 | 2 | 2019 |
| Generation of PUF-Keys on FPGAs by K-means frequency clustering KA Asha, A Patyal, HM Chen 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 44-49, 2018 | 2 | 2018 |
| On closing the gap between pre-simulation and post-simulation results in nanometer analog layouts PC Pan, HW Huang, CC Huang, A Patyal, HM Chen, TY Yang 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 2 | 2018 |
| On reducing lde variations in modern analog placement AK Thasreefa, A Patyal, HY Chi, MPH Lin, HM Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 1 | 2022 |
| On Reliability Hardening of FPGA based RO-PUF by using Regression Methodologies KA Asha, A Patyal, HM Chen 2023 International VLSI Symposium on Technology, Systems and Applications …, 2023 | | 2023 |
