| A CMOS Dual-Mode Brain–Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression H Pu, O Malekzadeh-Arasteh, AR Danesh, Z Nenadic, AH Do, P Heydari IEEE Journal of Solid-State Circuits 57 (6), 1824-1840, 2021 | 33 | 2021 |
| A 40V Voltage-Compliance 12.75 mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision H Pu, AR Danesh, O Malekzadeh-Arasteh, WJ Sohn, AH Do, Z Nenadic, ... 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 7 | 2021 |
| An Analysis of CMRR Degradation in Multi-Channel Biosignal Recording Systems O Malekzadeh-Arasteh, AR Danesh, AH Do, Z Nenadic, P Heydari IEEE Transactions on Circuits and Systems II: Express Briefs, 2020 | 5 | 2020 |
| A high-constant gm rail-to-rail operational amplifier using bump-smoothing technique with stabilized output stage R Dehghani, AR Danesh Analog Integrated Circuits and Signal Processing 103 (2020), 273-281, 2020 | 5 | 2020 |
| A digital arbitrary size kernel convolution smart image sensor based on in-pixel pulse width processors M Habibi, AR Danesh Sensor Review 37 (4), 468-477, 2017 | 3 | 2017 |
| A CMOS BD-BCI Incorporating Stimulation with Dual-Mode Charge Balancing and Time-Domain Pipelined Recording H Pu, AR Danesh, M Safiallah, J Lim, AH Do, Z Nenadic, P Heydari 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
| A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces O Malekzadeh-Arasteh, H Pu, AR Danesh, J Lim, PT Wang, CY Liu, ... 2021 43rd Annual International Conference of the IEEE Engineering in …, 2021 | 2 | 2021 |
| A Comprehensive Analysis of Charge-Pump-Based Multi-Stage Multi-Output DC-DC Converters AR Danesh, P Heydari 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 2 | 2021 |
| An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs AR Danesh, M Safiallah, H Pu, P Heydari IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 1 | 2023 |
| A CMOS BD-BCI: Neural Recorder with Two-Step Time-Domain Quantizer and Multi-Polar Stimulator with Dual-Mode Charge Balancing AR Danesh, H Pu, M Safiallah, AH Do, Z Nenadic, P Heydari IEEE Transactions on Biomedical Circuits and Systems, 2024 | | 2024 |
| High resolution electroencephalograph signal acquisition system A Danesh, P Heydari, H Pu, Z Nenadic, AH Do, O Malekzadeh Arasteh US Patent App. 18/245,120, 2023 | | 2023 |
| A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation M Safiallah, AR Danesh, H Pu, P Heydari IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | | 2023 |
| A signed pulse-train-based image processor-array for parallel kernel convolution in vision sensors AR Danesh, M Habibi Sensor Review 40 (4), 521-528, 2020 | | 2020 |
| Analog and Mixed Mode Circuits and Systems An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs......................... AR Danesh, M Safiallah, H Pu, P Heydari, K Xin, M Lai, F Lv, X Zheng, ... | | |
Payam HeydariChancellor’s Professor, University of CaliforniaVerified email at uci.edu
