Michele Franceschini
Title
Cited by
Cited by
Year
Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B, Nanotechnology and …, 2010
8812010
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
2009 42nd Annual IEEE/ACM international symposium on microarchitecture …, 2009
7412009
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
3182010
Morphable memory system: A robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Montaño, JP Karidis
ACM SIGARCH Computer Architecture News 38 (3), 153-162, 2010
2132010
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
1662012
Resistive memory devices having a not-and (NAND) structure
MJ Breitwisch, GS Ditlow, MM Franceschini, LA Lastras-Montano, ...
US Patent 8,107,276, 2012
1062012
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computer …, 2011
972011
Fundamental performance limits of communications systems impaired by impulse noise
R Pighi, M Franceschini, G Ferrari, R Raheli
IEEE Transactions on Communications 57 (1), 171-182, 2009
912009
Does the performance of LDPC codes depend on the channel?
M Franceschini, G Ferrari, R Raheli
IEEE Transactions on communications 54 (12), 2129-2132, 2006
772006
Transfer sheets
H Nakanishi
US Patent 6,878,423, 2005
70*2005
Iterative write pausing techniques to improve read latency of memory systems
MM Franceschini, LA Lastras-Montano, MK Qureshi, V Srinivasan
US Patent 8,004,884, 2011
672011
Serial concatenation of LDPC codes and differential modulations
M Franceschini, G Ferrari, R Raheli, A Curtoni
IEEE Journal on Selected Areas in Communications 23 (9), 1758-1768, 2005
652005
Adaptive endurance coding of non-volatile memories
MM Franceschini, A Jagmohan, JP Karidis, LA Lastras-Montano
US Patent 8,341,501, 2012
63*2012
Write amplification reduction in NAND flash through multi-write coding
A Jagmohan, M Franceschini, L Lastras
2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), 1-6, 2010
562010
Bad block management for flash memory
JA Bivens, MM Franceschini, A Jagmohan
US Patent 8,560,922, 2013
522013
LDPC coded modulations
M Franceschini, G Ferrari, R Raheli
Springer, 2009
482009
Estimation of closeness of topics based on graph analytics
MM Franceschini, A Jagmohan, LA Lastras-Montano, L Soares
US Patent 9,542,503, 2017
402017
Multi-Write endurance and error control coding of Non-Volatile memories
MM Franceschini, A Jagmohan
US Patent 8,769,374, 2014
402014
Non-volatile memories with enhanced write performance and endurance
MM Franceschini, A Jagmohan, LA Lastras-Montano, M Sharma
US Patent 8,176,235, 2012
402012
Architectural design for next generation heterogeneous memory systems
A Bivens, P Dube, M Franceschini, J Karidis, L Lastras, M Tsao
2010 IEEE International Memory Workshop, 1-4, 2010
402010
The system can't perform the operation now. Try again later.
Articles 1–20