| First monolithic integration of 3d complementary fet (cfet) on 300mm wafers S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ... 2020 Ieee Symposium on Vlsi Technology, 1-2, 2020 | 63 | 2020 |
| Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 48 | 2021 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 32 | 2020 |
| First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules S Yadav, KH Tan, KH Goh, S Subramanian, KL Low, N Chen, B Jia, ... 2015 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2015 | 20 | 2015 |
| Intel 4 CMOS technology featuring advanced FinFET transistors optimized for high density and high-performance computing B Sell, S An, J Armstrong, D Bahr, B Bains, R Bambery, K Bang, D Basu, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 18 | 2022 |
| Selective wet etching process for Ni-InGaAs contact formation in InGaAs N-MOSFETs with self-aligned source and drain S Subramanian, Q Zhou, X Zhang, M Balakrishnan, YC Yeo Journal of The Electrochemical Society 159 (1), H16, 2011 | 18 | 2011 |
| Genetic algorithm for embedding a complete graph in a hypercube with a VLSI application R Chandrasekharam, VV Vinod, S Subramanian Microprocessing and microprogramming 40 (8), 537-552, 1994 | 18 | 1994 |
| Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 16 | 2020 |
| N-channel InGaAs field-effect transistors formed on germanium-on-insulator substrates I Subramanian, MHS Owen, KH Tan, WK Loke, S Wicaksono, SF Yoon, ... Applied Physics Express 5 (11), 116502, 2012 | 12 | 2012 |
| Genetic algorithm for test scheduling with different objectives R Chandrasekharam, VV Vinod, S Subramanian Integration 17 (2), 153-161, 1994 | 12 | 1994 |
| Infrared spectroscopic ellipsometry study of sulfur-doped In0. 53Ga0. 47As ultra-shallow junctions V Richard D'Costa, S Subramanian, D Li, S Wicaksono, S Fatt Yoon, ... Applied Physics Letters 104 (23), 2014 | 8 | 2014 |
| CoInGaAs as a novel self-aligned metallic source/drain material for implant-less In0. 53Ga0. 47As n-MOSFETs EYJ Kong, S Subramanian, Q Zhou, J Pan, YC Yeo Solid-state electronics 78, 62-67, 2012 | 7 | 2012 |
| Embedded Metal Source/Drain (eMSD) for series resistance reduction in In0.53Ga0.47As n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET) S Subramanian, YC Yeo Proceedings of Technical Program of 2012 VLSI Technology, System and …, 2012 | 7 | 2012 |
| Ultra-thin-body In0.7Ga0.3As-on-nothing N-MOSFET with Pd-InGaAs source/drain contacts enabled by a new self-aligned cavity formation technology X Gong, Z Zhu, E Kong, R Cheng, S Subramanian, KH Goh, YC Yeo Proceedings of Technical Program of 2012 VLSI Technology, System and …, 2012 | 7 | 2012 |
| Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes AP Peter, T Tomomi, E Taishi, S Eiichiro, A Sepulveda, T Blanquart, ... Journal of Vacuum Science & Technology A 39 (4), 2021 | 6 | 2021 |
| P2S5/(NH4)2Sx-Based Sulfur Monolayer Doping for Source/Drain Extensions in n-Channel InGaAs FETs S Subramanian, EYJ Kong, D Li, S Wicaksono, SF Yoon, YC Yeo IEEE Transactions on Electron Devices 61 (8), 2767-2773, 2014 | 6 | 2014 |
| FinFETs with thermally stable RMG gate stack for future DRAM peripheral circuits E Capogreco, H Arimura, R Ritzenthaler, S Brus, Y Oniki, E Dupuy, ... 2022 International Electron Devices Meeting (IEDM), 26.2. 1-26.2. 4, 2022 | 4 | 2022 |
| A control constrained test scheduling approach for VLSI circuits S Misra, S Subramanian, PP Chaudhuri Proceedings First Asian Test Symposium, 145,146,147,148,149,150-145,146,147 …, 1992 | 4 | 1992 |
| Buried power rail integration for CMOS scaling beyond the 3 nm node A Gupta, Z Tao, D Radisic, H Mertens, OV Pedreira, S Demuynck, ... Advanced Etch Technology and Process Integration for Nanopatterning XI 12056 …, 2022 | 3 | 2022 |
| Plasma doping of InGaAs at elevated substrate temperature for reduced sheet resistance and defect formation EYJ Kong, S Subramanian, VR D’Costa, LH Chua, W Zou, C Chan, ... IEEE Transactions on Electron Devices 61 (9), 3159-3165, 2014 | 3 | 2014 |
