Adrią Armejach
Adrią Armejach
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EazyHTM: Eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
An empirical evaluation of high-level synthesis languages and tools for database acceleration
O Arcas-Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory
A Armejach, A Seyedi, R Titos-Gil, I Hur, OS Unsal, M Valero
2011 International Conference on Parallel Architectures and Compilation …, 2011
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory
A Armejach, A Negi, A Cristal, O Unsal, P Stenstrom, T Harris
20th Annual International Conference on High Performance Computing, 196-205, 2013
Hardware acceleration for query processing: leveraging FPGAs, CPUs, and memory
O Arcas-Abella, A Armejach, T Hayes, GA Malazgirt, O Palomar, B Salami, ...
Computing in Science & Engineering 18 (1), 80-87, 2016
Stencil codes on a vector length agnostic architecture
A Armejach, H Caminal, JM Cebrian, R Gonzįlez-Alberquilla, ...
Proceedings of the 27th International Conference on Parallel Architectures …, 2018
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
Using Arm’s scalable vector extension on stencil codes
A Armejach, H Caminal, JM Cebrian, R Langarita, R Gonzįlez-Alberquilla, ...
The Journal of Supercomputing 76 (3), 2039-2062, 2020
Techniques to improve performance in requester-wins hardware transactional memory
A Armejach, R Titos-Gil, A Negi, OS Unsal, A Cristal
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-25, 2013
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
Implications of non-volatile memory as primary storage for database management systems
NU Mustafa, A Armejach, O Ozturk, A Cristal, OS Unsal
2016 International Conference on Embedded Computer Systems: Architectures …, 2016
Towards resilient EU HPC systems: A blueprint
P Radojkovic, M Marazakis, P Carpenter, R Jeyapaul, D Gizopoulos, ...
European HPC resilience initiative, 2020
Tidy cache: Improving data placement in die-stacked DRAM caches
A Armejach, A Cristal, OS Unsal
2015 27th International Symposium on Computer Architecture and High …, 2015
An empirical evaluation of high-level synthesis languages and tools for database acceleration
OA Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, J Navaridas, ...
The Institute of Electrical and Electronics Engineers, Inc, 2014
Novel SRAM bias control circuits for a low power L1 data cache
A Seyedi, A Armejach, A Cristal, OS Unsal, M Valero
NORCHIP 2012, 1-6, 2012
Transactional prefetching: Narrowing the window of contention in hardware transactional memory
A Negi, A Armejach, A Cristal, OS Unsal, P Stenstrom
Proceedings of the 21st international conference on Parallel architectures …, 2012
Compressed sparse FM-index: Fast sequence alignment using large k-steps
R Langarita, A Armejach, J Setoain, PEI Marin, J Alastruey-Benede, ...
IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2020
Design trade-offs for emerging HPC processors based on mobile market technology
A Armejach, M Casas, M Moretó
The Journal of Supercomputing 75 (9), 5717-5740, 2019
Design space exploration of next-generation HPC machines
C Gómez, F Martınez, A Armejach, M Moretó, F Mantovani, M Casas
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
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