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Chuck Alpert
Chuck Alpert
Senior Software Architect, Cadence Design Systems
Verifierad e-postadress på cadence.com
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Recent directions in netlist partitioning: A survey
CJ Alpert, AB Kahng
Integration 19 (1-2), 1-81, 1995
9421995
The ISPD98 circuit benchmark suite
CJ Alpert
Proceedings of the 1998 international symposium on Physical design, 80-85, 1998
4331998
Multilevel circuit partitioning
CJ Alpert, JH Huang, AB Kahng
Proceedings of the 34th annual Design Automation Conference, 530-533, 1997
4011997
A clock distribution network for microprocessors
PJ Restle, TG McNamara, DA Webber, PJ Camporese, KF Eng, ...
IEEE Journal of Solid-State Circuits 36 (5), 792-799, 2001
3732001
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
3222008
Buffer insertion for noise and delay optimization
CJ Alpert, A Devgan, ST Quay
Proceedings of the 35th annual Design Automation Conference, 362-367, 1998
2931998
Wire segmenting for improved buffer insertion
C Alpert, A Devgan
Proceedings of the 34th Annual Design Automation Conference, 588-593, 1997
2921997
Spectral partitioning: The more eigenvectors, the better
CJ Alpert, SZ Yao
Proceedings of the 32nd annual ACM/IEEE design automation conference, 195-200, 1995
2671995
Spectral partitioning with multiple eigenvectors
CJ Alpert, AB Kahng, SZ Yao
Discrete Applied Mathematics 90 (1-3), 3-26, 1999
2291999
A practical methodology for early buffer and wire resource allocation
CJ Alpert, J Hu, SS Sapatnekar, P Villarrubia
Proceedings of the 38th annual Design Automation Conference, 189-194, 2001
193*2001
RC delay metrics for performance optimization
CJ Alpert, A Devgan, CV Kashyap
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
1752001
The ISPD2005 placement contest and benchmark suite
GJ Nam, CJ Alpert, P Villarrubia, B Winter, M Yildiz
Proceedings of the 2005 international symposium on Physical design, 216-220, 2005
1652005
Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation
CJ Alpert, A Devgan, ST Quay
US Patent 6,347,393, 2002
1442002
Optimum buffer placement for noise avoidance
CJ Alpert, ST Quay, A Devgan
US Patent 6,117,182, 2000
1442000
Buffer insertion with accurate gate and interconnect delay computation
CJ Alpert, A Devgan, ST Quay
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 479-484, 1999
1431999
The ISPD-2011 routability-driven placement contest and benchmark suite
N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy
Proceedings of the 2011 international symposium on Physical design, 141-146, 2011
1152011
Porosity aware buffered steiner tree construction
CJ Alpert, RG Gandham, J Hu, ST Quay
US Patent 7,065,730, 2006
1132006
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
CJ Alpert, TC Hu, JH Huang, AB Kahng, D Karger
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
1111995
The DAC 2012 routability-driven placement contest and benchmark suite
N Viswanathan, C Alpert, C Sze, Z Li, Y Wei
Proceedings of the 49th Annual Design Automation Conference, 774-782, 2012
1062012
A semi-persistent clustering technique for VLSI circuit placement
C Alpert, A Kahng, GJ Nam, S Reda, P Villarrubia
Proceedings of the 2005 international symposium on Physical design, 200-207, 2005
1052005
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Artiklar 1–20