Vivek Tiwari
Titel
Citeras av
Citeras av
År
Wattch: A framework for architectural-level power analysis and optimizations
D Brooks, V Tiwari, M Martonosi
ACM SIGARCH Computer Architecture News 28 (2), 83-94, 2000
35862000
Power analysis of embedded software: a first step towards software power minimization
V Tiwari, S Malik, A Wolfe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (4), 437-445, 1994
14271994
Instruction level power analysis and optimization of software
V Tiwari, S Malik, A Wolfe, MTC Lee
Technologies for wireless computing, 139-154, 1996
7551996
Reducing power in high-performance microprocessors
V Tiwari, D Singh, S Rajgopal, G Mehta, R Patel, F Baez
Proceedings of the 35th annual Design Automation Conference, 732-737, 1998
4891998
Power analysis and minimization techniques for embedded DSP software
MTC Lee, V Tiwari, S Malik, M Fujita
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (1), 123-135, 1997
3561997
Compilation techniques for low energy: An overview
V Tiwari, S Malik, A Wolfe
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium, 38-39, 1994
2941994
Guarded evaluation: Pushing power management to logic synthesis/design
V Tiwari, S Malik, P Ashar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
2561998
Technology mapping for low power
V Tiwari, P Ashar, S Malik
Design Automation, 1993. 30th Conference on, 74-79, 1993
193*1993
Power analysis of a 32-bit embedded microcontroller
V Tiwari, MTC Lee
VLSI Design 7 (3), 225-242, 1998
1221998
Microarchitectural simulation and control of di/dt-induced power supply voltage variation
E Grochowski, D Ayers, V Tiwari
High-Performance Computer Architecture, 2002. Proceedings. Eighth …, 2002
1022002
Multiple mode power throttle mechanism
JS Burns, S Rusu, DJ Ayers, ET Grochowski, M Eng, V Tiwari
US Patent 6,931,559, 2005
972005
Power analysis and low-power scheduling techniques for embedded DSP software
MTC Lee, V Tiwari, S Malik, M Fujita
Proceedings of the 8th international symposium on System synthesis, 110-115, 1995
811995
Mechanism to control di/dt for a microprocessor
ET Grochowski, D Sager, V Tiwari, I Young, DJ Ayers
US Patent 6,636,976, 2003
692003
Digital throttle for multiple operating points
JS Burns, S Rusu, DJ Ayers, ET Grochowski, M Eng, V Tiwari
US Patent 7,281,140, 2007
622007
An architectural solution for the inductive noise problem due to clock-gating
MD Pant, P Pant, DS Wills, V Tiwari
Proceedings of the 1999 international symposium on Low power electronics and …, 1999
591999
Topological analysis for leakage prediction of digital circuits
W Jiang, V Tiwari, E Iglesia, A Sinha
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, 39, 2002
582002
Dynamic power management for microprocessors: A case study
V Tiwari, R Donnelly, S Malik, R Gonzalez
VLSI Design, 1997. Proceedings., Tenth International Conference on, 185-192, 1997
421997
Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages
V Tiwari, V Sharma, S Makineni, SB Medapati
US Patent 6,609,209, 2003
412003
Inductive noise reduction at the architectural level
MD Pant, P Pant, DS Wills, V Tiwari
VLSI Design, 2000. Thirteenth International Conference on, 162-167, 2000
322000
Logic and system design for low power consumption
V Tiwari
Princeton University, 1996
291996
Systemet kan inte utföra åtgärden just nu. Försök igen senare.
Artiklar 1–20