Rajat Subhra Chakraborty
Rajat Subhra Chakraborty
Associate Professor, Dept. of Computer Science and Engineering, IIT Kharagpur, India - 721302
Verified email at cse.iitkgp.ac.in - Homepage
Title
Cited by
Cited by
Year
MERO: A Statistical Approach for Hardware Trojan Detection
RS Chakraborty, F Wolff, S Paul, C Papachristou, S Bhunia
International Workshop on Cryptographic Hardware and Embedded Systems, 396-410, 2009
4282009
Hardware Trojan: Threats and emerging solutions
RS Chakraborty, S Narasimhan, S Bhunia
2009 IEEE International high level design validation and test workshop, 166-171, 2009
4272009
HARPOON: An obfuscation-based SoC design methodology for hardware protection
RS Chakraborty, S Bhunia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
4102009
Towards Trojan-free trusted ICs: Problem analysis and detection scheme
F Wolff, C Papachristou, S Bhunia, RS Chakraborty
2008 Design, Automation and Test in Europe, 1362-1365, 2008
3852008
Security against hardware Trojan through a novel application of design obfuscation
RS Chakraborty, S Bhunia
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
2102009
Hardware Trojan detection by multiple-parameter side-channel analysis
S Narasimhan, D Du, RS Chakraborty, S Paul, FG Wolff, CA Papachristou, ...
IEEE Transactions on computers 62 (11), 2183-2195, 2012
1962012
Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach
S Narasimhan, D Du, RS Chakraborty, S Paul, F Wolff, C Papachristou, ...
2010 IEEE international symposium on hardware-oriented security and trust …, 2010
1562010
Hardware protection and authentication through netlist level obfuscation
RS Chakraborty, S Bhunia
2008 IEEE/ACM International Conference on Computer-Aided Design, 674-677, 2008
1482008
On-demand transparency for improving hardware Trojan detectability
RS Chakraborty, S Paul, S Bhunia
2008 IEEE International Workshop on Hardware-Oriented Security and Trust, 48-50, 2008
1362008
Self-referencing: A scalable side-channel approach for hardware Trojan detection
D Du, S Narasimhan, RS Chakraborty, S Bhunia
International Workshop on Cryptographic Hardware and Embedded Systems, 173-187, 2010
1232010
TeSR: A robust temporal self-referencing approach for hardware Trojan detection
S Narasimhan, X Wang, D Du, RS Chakraborty, S Bhunia
2011 IEEE International Symposium on Hardware-Oriented Security and Trust, 71-74, 2011
1192011
Hardware Trojan insertion by direct modification of FPGA configuration bitstream
RS Chakraborty, I Saha, A Palchaudhuri, GK Naik
IEEE Design & Test 30 (2), 45-54, 2013
1162013
VIm-Scan: A low overhead scan design approach for protection of secret key in scan-based secure chips
S Paul, RS Chakraborty, S Bhunia
25th IEEE VLSI Test Symposium (VTS'07), 455-460, 2007
1132007
RTL hardware IP protection using key-based control and data flow obfuscation
RS Chakraborty, S Bhunia
2010 23rd International Conference on VLSI Design, 405-410, 2010
1052010
Security against hardware Trojan attacks using key-based design obfuscation
RS Chakraborty, S Bhunia
Journal of Electronic Testing 27 (6), 767-785, 2011
852011
Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability
S Saha, RS Chakraborty, SS Nuthakki, D Mukhopadhyay
International Workshop on Cryptographic Hardware and Embedded Systems, 577-596, 2015
832015
Building PUF based authentication and key exchange protocol for IoT without explicit CRPs in verifier database
U Chatterjee, V Govindan, R Sadhukhan, D Mukhopadhyay, ...
IEEE transactions on dependable and secure computing 16 (3), 424-437, 2018
762018
A PUF-based secure communication protocol for IoT
U Chatterjee, RS Chakraborty, D Mukhopadhyay
ACM Transactions on Embedded Computing Systems (TECS) 16 (3), 1-25, 2017
762017
A PUF-enabled secure architecture for FPGA-based IoT applications
AP Johnson, RS Chakraborty, D Mukhopadhyay
IEEE Transactions on Multi-Scale Computing Systems 1 (2), 110-122, 2015
682015
Protection of intellectual property cores through a design flow
RS Chakraborty, S Narasimhan, S Bhunia
US Patent 8,402,401, 2013
622013
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