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Dae-Hyun Kim
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AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
2402015
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
2182013
Architectural support for mitigating row hammering in dram memories
DH Kim, P Nair, M Qureshi
Computer Architecture Letters 14 (1), 9-12, 2015
1642015
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion
SJ Bae, KI Park, JD Ihm, HY Song, WJ Lee, HJ Kim, KH Kim, YS Park, ...
IEEE journal of solid-state circuits 43 (1), 121-131, 2008
812008
A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques
SJ Bae, YS Sohn, KI Park, KH Kim, DH Chung, JG Kim, SH Kim, MS Park, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
602008
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
SJ Bae, YS Sohn, TY Oh, SH Kim, YS Yang, DH Kim, SH Kwak, HS Seol, ...
2011 IEEE international solid-state circuits conference, 498-500, 2011
392011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM with 2.5 ns bank to bank active time and no bank group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
IEEE journal of solid-state circuits 46 (1), 107-118, 2010
302010
Photo-assisted electrochemical etching of a nano-gap trench with high aspect ratio for MEMS applications
HC Kim, DH Kim, K Chun
Journal of Micromechanics and Microengineering 16 (5), 906, 2006
272006
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion
JD Ihm, SJ Bae, KI Park, HY Song, WJ Lee, HJ Kim, KH Kim, HK Lee, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
262007
25.2 A 16Gb Sub-1V 7.14 Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body …
YH Kim, HJ Kim, J Choi, MS Ahn, D Lee, SH Cho, DY Park, YJ Park, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 346-348, 2021
192021
Method of training memory core and memory system
WJ Lee, DH Kim, SJ Bae, YS Sohn, TY Oh
US Patent App. 13/941,359, 2014
192014
A 7Gb/s/pin GDDR5 SDRAM with 2.5 ns bank-to-bank active time and no bank-group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 434-435, 2010
192010
A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface
SJ Bae, YS Sohn, T Oh, SH Kwak, DM Kim, DH Kim, YS Kim, YS Yang, ...
2010 Symposium on VLSI Circuits, 193-194, 2010
182010
22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020
172020
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs
DH Kim, L Milor
VLSI Test Symposium (VTS), 2016 IEEE 34th, 1-6, 2016
152016
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
W Kim, CC Chen, DH Kim, L Milor
Transactions on Very Large Scale Integration (VLSI) Systems 24 (7), 2521-2534, 2016
132016
Data receiver having an integration unit and a sense amplification unit, and semiconductor memory device including the same
DH Kim, SJ Bae
US Patent 8,467,255, 2013
112013
A 16Gb 9.5Gb/s/pin LPDDR5X SDRAM with Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm …
DH Kim, B Song, H Ahn, W Ko, S Do, S Cho, K Kim, SH Oh, HY Joo, ...
IEEE International Solid-State Circuits Conference, 2022
102022
Semiconductor memory devices and memory systems including the same
DH Kim, YK Joo, JJ Kong, K Lee, MK Lee
US Patent 11,036,578, 2019
102019
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits
K Yang, T Liu, R Zhang, DH Kim, L Milor
Microelectronics Reliability 76, 81-86, 2017
102017
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