| Community networks: the Internet by the people, for the people L Belli, SB Belur, P Bloom, A Esterhuysen, N Foditsch, M Hernandez, ... FGV Direito Rio, 2017 | 29 | 2017 |
| A detailed characterization of errors in logic circuits due to single-event transients NP Rao, MP Desai 2015 Euromicro Conference on Digital System Design, 714-721, 2015 | 15 | 2015 |
| 11.3: Wavelets for Displaying Gray Shades in LCDs TN Ruckmongathan, PN Rao, A Prasad SID Symposium Digest of Technical Papers 36 (1), 168-171, 2005 | 13 | 2005 |
| Community-led Networks for Sustainable Rural Broadband in India: the Case of Gram Marg SB Belur, M Khaturia, NP Rao Community Networks: the Internet by the People, for the People, 193, 2017 | 8 | 2017 |
| An automated approach to compare bit serial and bit parallel in-memory computing for dnns A Parmar, K Prasad, N Rao, J Mekie 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2948-2952, 2022 | 4 | 2022 |
| Flush-reload attack and its mitigation on an fpga based compressed cache design P Mata, N Rao 2021 22nd International Symposium on Quality Electronic Design (ISQED), 535-541, 2021 | 4 | 2021 |
| Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates NP Rao, MP Desai arXiv preprint arXiv:1612.08239, 1-6, 2016 | 3 | 2016 |
| On the likelihood of multiple bit upsets in logic circuits NP Rao, S Sarik, MP Desai arXiv preprint arXiv:1401.1003, 2014 | 3 | 2014 |
| The characterization of errors in an FPGA-based RISC-V processor due to single event transients J Sharma, N Rao Microelectronics Journal 123, 105392, 2022 | 2 | 2022 |
| FastMem: a fast architecture-aware memory layout design A Parmar, K Prasad, N Rao, J Mekie 2022 23rd International Symposium on Quality Electronic Design (ISQED), 120-126, 2022 | 2 | 2022 |
| Community-led Networks for Sustainable Rural Broadband in India: the Case of Gram Marg S BANERJEE BELUR, M KHATURIA, P RAO, NANDITHA CNs: the Internet by the People, for the People, 2017 | 2 | 2017 |
| Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits NP Rao, MP Desai arXiv preprint arXiv:1612.08239, 2016 | 2 | 2016 |
| An FPGA based tiled systolic array generator to accelerate CNNs VS Devaraddi, N Rao 2022 25th Euromicro Conference on Digital System Design (DSD), 316-323, 2022 | 1 | 2022 |
| Variable Bit-Precision Vector Extension for RISC-V Based Processors SSNR Risikesh R k 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on …, 2021 | 1 | 2021 |
| Fault Injection Controller Based Framework to Characterize Multiple Bit Upsets for FPGA Designs J Sharma, N Rao, OA Mohamed 2020 IEEE International Symposium on the Physical and Failure Analysis of …, 2020 | 1 | 2020 |
| MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA S Shah, NP Rao Proceedings of the Great Lakes Symposium on VLSI 2023, 155-158, 2023 | | 2023 |
| DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision A Mishra, N Rao 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023 | | 2023 |
| Enhancing Convolution Throughput with Vector Systolic Architecture on FPGA J Shah, N Rao International Conference on Parallel Architectures and Compilation …, 2023 | | 2023 |
| A Framework for Frequency Optimized Linear Scalable Architec- ture for CNN Inference on FPGAs S Das, N Rao, S Sinha Design Automation Conference (DAC) IP Track, 2023 | | 2023 |
| Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks A Mishra, N Rao, GG Gore, X Tang IEEE Asia Pacific Circuits and Systems (APCCAS), 2023 | | 2023 |
Madhav Desaiprofessor of electrical engineering, indian institute of technology bombayVerifierad e-postadress på ee.iitb.ac.in
