| Novel forksheet device architecture as ultimate logic scaling device towards 2nm P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ... 2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019 | 90 | 2019 |
| Enabling sub-5nm CMOS technology scaling thinner and taller! J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ... 2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019 | 67 | 2019 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 64 | 2019 |
| Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 48 | 2021 |
| Introducing 2D-FETs in device scaling roadmap using DTCO Z Ahmed, A Afzalian, T Schram, D Jang, D Verreck, Q Smets, ... 2020 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2020 | 35 | 2020 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 32 | 2020 |
| A comprehensive study of nanosheet and forksheet SRAM for beyond N5 node MK Gupta, P Weckx, P Schuddinck, D Jang, B Chehab, S Cosemans, ... IEEE Transactions on Electron Devices 68 (8), 3819-3825, 2021 | 30 | 2021 |
| PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 17 | 2022 |
| IR-drop analysis of hybrid bonded 3D-ICs with backside power delivery and μ-& n-TSVs G Sisto, B Chehab, B Genneret, R Baert, R Chen, P Weckx, J Ryckaert, ... 2021 IEEE International Interconnect Technology Conference (IITC), 1-3, 2021 | 17 | 2021 |
| Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 16 | 2020 |
| The Complementary FET (CFET) 6T-SRAM MK Gupta, P Weckx, P Schuddinck, D Jang, B Chehab, S Cosemans, ... IEEE Transactions on Electron Devices 68 (12), 6106-6111, 2021 | 13 | 2021 |
| Application of cell-aware test on an advanced 3nm CMOS technology library Z Gao, S Malagi, MC Hu, J Swenton, R Baert, J Huisken, B Chehab, ... 2019 IEEE International Test Conference (ITC), 1-6, 2019 | 13 | 2019 |
| Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm B Chehab, J Ryckaert, P Schuddinck, P Weckx, N Horiguchi, G Mirabelli, ... Design-Process-Technology Co-optimization XV 11614, 59-63, 2021 | 12 | 2021 |
| Design and optimization of SRAM macro and logic using backside interconnects at 2nm node R Chen, G Sisto, A Jourdain, G Hiblot, M Stucchi, N Kakarla, B Chehab, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.4. 1-22.4. 4, 2021 | 11 | 2021 |
| From design to system-technology optimization for CMOS J Ryckaert, B Chehab, D Jang, G Mirabelli, SM Salahuddin, P Schuddinck, ... 2021 International Symposium on VLSI Technology, Systems and Applications …, 2021 | 10 | 2021 |
| Buried power rail scaling and metal assessment for the 3 nm node and beyond A Gupta, OV Pedreira, Z Tao, H Mertens, D Radisic, N Jourdan, ... 2020 IEEE International Electron Devices Meeting (IEDM), 20.3. 1-20.3. 4, 2020 | 10 | 2020 |
| Buried power rail metal exploration towards the 1 nm node A Gupta, D Radisic, JW Maes, OV Pedreira, JP Soulié, N Jourdan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2021 | 9 | 2021 |
| Standard cell architectures for N2 node: transition from FinFET to nanosheet and to forksheet device B Chehab, P Weckx Sr, J Ryckaert Sr, D Jang Sr, D Verkest, A Spessot Design-Process-Technology Co-optimization for Manufacturability XIV 11328, 28-35, 2020 | 7 | 2020 |
| Extended scale length theory targeting low-dimensional FETs for carbon nanotube FET digital logic design-technology co-optimization C Gilardi, B Chehab, G Sisto, P Schuddinck, Z Ahmed, O Zografos, Q Lin, ... 2021 IEEE International Electron Devices Meeting (IEDM), 27.3. 1-27.3. 4, 2021 | 6 | 2021 |
| Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node B Chehab, O Zografos, ED Litta, Z Ahmed, P Schuddinck, D Jang, ... 2021 IEEE International Interconnect Technology Conference (IITC), 1-3, 2021 | 5 | 2021 |
