Nodari Sitchinava
Nodari Sitchinava
Verified email at hawaii.edu - Homepage
Title
Cited by
Cited by
Year
Sorting, searching, and simulation in the mapreduce framework
MT Goodrich, N Sitchinava, Q Zhang
International Symposium on Algorithms and Computation, 374-383, 2011
1872011
Fundamental parallel algorithms for private-cache chip multiprocessors
L Arge, MT Goodrich, M Nelson, N Sitchinava
Proceedings of the twentieth annual symposium on Parallelism in algorithms …, 2008
1472008
A reconfigurable shared scan-in architecture
S Samaranayake, E Gizdarski, N Sitchinava, F Neuveux, R Kapur, ...
Proceedings. 21st VLSI Test Symposium, 2003., 9-14, 2003
1132003
Changing the scan enable during shift
N Sitchinava, E Gizdarski, S Samaranayake, F Neuveux, R Kapur, ...
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 73-78, 2004
882004
Parallel external memory graph algorithms
L Arge, MT Goodrich, N Sitchinava
2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010
412010
Guard placement for efficient point-in-polygon proofs
D Eppstein, MT Goodrich, N Sitchinava
Proceedings of the twenty-third annual symposium on Computational geometry …, 2007
40*2007
Dynamic scan: Driving down the cost of test
S Samaranayake, N Sitchinava, R Kapur, MB Amin, TW Williams
Computer 35 (10), 63-68, 2002
352002
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, F Neuveux, ...
US Patent 7,418,640, 2008
252008
Lower bounds in the asymmetric external memory model
R Jacob, N Sitchinava
Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and …, 2017
242017
Efficient parallel and external matching
M Birn, V Osipov, P Sanders, C Schulz, N Sitchinava
European Conference on Parallel Processing, 659-670, 2013
232013
Geometric algorithms for private-cache chip multiprocessors
D Ajwani, N Sitchinava, N Zeh
European Symposium on Algorithms, 75-86, 2010
182010
Provably efficient GPU algorithms
N Sitchinava, V Weichert
CoRR, abs/1306.5076, 2013
162013
A parallel buffer tree
N Sitchinava, N Zeh
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in …, 2012
162012
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ...
US Patent 7,743,299, 2010
152010
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ...
US Patent 7,596,733, 2009
132009
On the complexity of list ranking in the parallel external memory model
R Jacob, T Lieber, N Sitchinava
International Symposium on Mathematical Foundations of Computer Science, 384-395, 2014
122014
Analysis-driven engineering of comparison-based sorting algorithms on GPUs
B Karsin, V Weichert, H Casanova, J Iacono, N Sitchinava
Proceedings of the 2018 International Conference on Supercomputing, 86-95, 2018
102018
On (dynamic) range minimum queries in external memory
L Arge, J Fischer, P Sanders, N Sitchinava
Workshop on Algorithms and Data Structures, 37-48, 2013
92013
Sorting and permuting without bank conflicts on GPUs
P Afshani, N Sitchinava
Algorithms-ESA 2015, 13-24, 2015
82015
Efficient batched predecessor search in shared memory on GPUs
B Karsin, H Casanova, N Sitchinava
2015 IEEE 22nd International Conference on High Performance Computing (HiPC …, 2015
72015
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Articles 1–20