Thien Truong NGUYEN LY
Thien Truong NGUYEN LY
PhD student, CEA-LETI
Verifierad e-postadress på cea.fr
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FPGA design of high throughput LDPC decoder based on imprecise offset min-sum decoding
T Nguyen-Ly, K Le, F Ghaffari, A Amaricai, O Boncalo, V Savin, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
352015
Flexible, cost-efficient, high-throughput architecture for layered LDPC decoders with fully-parallel processing units
TT Nguyen-Ly, T Gupta, M Pezzin, V Savin, D Declercq, S Cotofana
2016 Euromicro Conference on Digital System Design (DSD), 230-237, 2016
252016
Analysis and design of cost-effective, high-throughput LDPC decoders
TT Nguyen-Ly, V Savin, K Le, D Declercq, F Ghaffari, O Boncalo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 508-521, 2017
222017
Non-surjective finite alphabet iterative decoders
TT Nguyen-Ly, K Le, V Savin, D Declercq, F Ghaffari, O Boncalo
2016 IEEE International Conference on Communications (ICC), 1-6, 2016
152016
High throughput FPGA implementation for regular non-surjective finite alphabet iterative decoders
TT Nguyen-Ly, V Savin, X Popon, D Declercq
2017 IEEE International Conference on Communications Workshops (ICC …, 2017
82017
Code-aware quantizer design for finite-precision min-sum decoders
Z Mheich, TT Nguyen-Ly, V Savin, D Declercq
2016 IEEE International Black Sea Conference on Communications and …, 2016
52016
Efficient hardware implementations of ldpc decoders, through exploiting impreciseness in message-passing decoding algorithms
TTN Ly
22017
Design and Implementation of a SoPC System for Speech Recognition
VH Tran, LTT Nguyen, T Hoang, XT Tran
Springer Netherlands, 2013
22013
FPGA architecture of HMM-based decoder module in speech recognizer
T Hoang, VV Quoc, TNL Thien
2012 International Conference on Control, Automation and Information …, 2012
22012
Low-cost, high-efficiency hardware implementation of smart traffic light system
TT Nguyen-Ly, L Tran, TV Huynh
2019 International Symposium on Electrical and Electronics Engineering (ISEE …, 2019
12019
Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul
TT Nguyen Ly
Cergy-Pontoise, 2017
2017
VLSI ARCHITECTURE OF MAGNITUDE ESTIMATION ALGORITHM FOR SPEECH RECOGNITION SYSTEM
NLT Truong, H Trang
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Artiklar 1–12