Zhuo Li
Zhuo Li
Software Engineering Director, Cadence
Verifierad e-postadress på cadence.com - Startsida
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K longest paths per gate (KLPG) test generation for scan-based sequential circuits
W Qiu, J Wang, DMH Walker, D Reddy, X Lu, Z Li, W Shi, H Balachandran
2004 International Conferce on Test, 223-231, 2004
1442004
A fast algorithm for optimal buffer insertion
W Shi, Z Li
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2005
116*2005
The ISPD-2011 routability-driven placement contest and benchmark suite
N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy
Proceedings of the 2011 international symposium on Physical design, 141-146, 2011
1052011
High prevalence of dyslipidemia and associated risk factors among rural Chinese adults
GZ Sun, Z Li, L Guo, Y Zhou, HM Yang, YX Sun
Lipids in health and disease 13 (1), 1-11, 2014
1032014
Longest-path selection for delay test under process variation
X Lu, Z Li, W Qiu, DMH Walker, W Shi
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2005
982005
Fast algorithms for slew-constrained minimum cost buffering
S Hu, CJ Alpert, J Hu, SK Karandikar, Z Li, W Shi, CN Sze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
952007
New placement prediction and mitigation techniques for local routing congestion
T Taghavi, Z Li, C Alpert, GJ Nam, A Huber, S Ramji
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on …, 2010
942010
Timing refinement re-routing
MA Kazda, Z Li, GJ Nam, Y Zhou
US Patent 8,635,577, 2014
892014
The DAC 2012 routability-driven placement contest and benchmark suite
N Viswanathan, C Alpert, C Sze, Z Li, Y Wei
DAC Design Automation Conference 2012, 774-782, 2012
862012
GLARE: Global and local wiring aware routability evaluation
Y Wei, C Sze, N Viswanathan, Z Li, CJ Alpert, L Reddy, AD Huber, ...
DAC Design Automation Conference 2012, 768-773, 2012
822012
Techniques for fast physical synthesis
CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ...
Proceedings of the IEEE 95 (3), 573-599, 2007
812007
A circuit level fault model for resistive opens and bridges
Z Li, X Lu, W Qiu, W Shi, DMH Walker
Proceedings. 21st VLSI Test Symposium, 2003., 379-384, 2003
762003
Methodology for standard cell compliance and detailed placement for triple patterning lithography
B Yu, X Xu, JR Gao, Y Lin, Z Li, CJ Alpert, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
742015
What makes a design difficult to route
CJ Alpert, Z Li, MD Moffitt, GJ Nam, JA Roy, G Tellez
Proceedings of the 19th international symposium on Physical design, 7-12, 2010
742010
Fast interconnect synthesis with layer assignment
Z Li, CJ Alpert, S Hu, T Muhmud, ST Quay, PG Villarrubia
Proceedings of the 2008 international symposium on Physical design, 71-77, 2008
55*2008
MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes
Y Lin, B Yu, X Xu, JR Gao, N Viswanathan, WH Liu, Z Li, CJ Alpert, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
482017
RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm
DA Papa, T Luo, MD Moffitt, CN Sze, Z Li, GJ Nam, CJ Alpert, IL Markov
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2008
482008
Probabilistic congestion prediction with partial blockages
Z Li, CJ Alpert, ST Quay, S Sapatnekar, W Shi
Quality Electronic Design, 2007. ISQED'07. 8th International Symposium on …, 2007
47*2007
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
W Shi, Z Li, CJ Alpert
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004
472004
Physical synthesis with clock-network optimization for large systems on chips
D Papa, C Alpert, C Sze, Z Li, N Viswanathan, GJ Nam, I Markov
IEEE Micro 31 (4), 51-62, 2011
462011
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Artiklar 1–20