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Dr. Adhithan Pon
Dr. Adhithan Pon
Researcher @ TCS (R&D)
No verified email
Title
Cited by
Cited by
Year
Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET
A Pon, KSVP Tulasi, R Ramesh
AEU-International Journal of Electronics and Communications 102, 1-8, 2019
272019
Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor
A Pon, AS Carmel, A Bhattacharyya, R Ramesh
Superlattices and Microstructures 113, 608-615, 2018
132018
Recent developments in black phosphorous transistors: a review
A Pon, A Bhattacharyya, R Rathinam
Journal of Electronic Materials, 1-17, 2021
122021
Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application
R Rathinam, A Pon, S Carmel, A Bhattacharyya
IET Circuits, Devices & Systems 14 (8), 1167-1172, 2020
102020
Simulation of 2D Layered Material Ballistic FETs using a Hybrid Methodology
RR Adhithan Pon,Santhia Carmel,Arkaprava Bhattacharyya
International Conference on Electron Devices and Solid-State Circuits (EDSSC …, 2019
7*2019
Bandgap scaling and negative differential resistance behavior of zigzag phosphorene antidot nanoribbons (ZPANRs)
S Carmel, A Pon, N Meenakshisundaram, R Ramesh, A Bhattacharyya
Physical Chemistry Chemical Physics 20 (21), 14855-14863, 2018
62018
Optimization of the geometry of a charge plasma double-gate junctionless transistor for improved RF stability
A Pon, A Bhattacharyya, B Padmanaban, R Ramesh
Journal of Computational Electronics 18, 906-917, 2019
52019
Charge plasma-based phosphorene tunnel FET using a hybrid computational method
A Pon, A Bhattacharyya, R Ramesh
Journal of Electronic Materials 50, 3624-3633, 2021
42021
Insights on Si doping on PNRs for NDR with high PVR and diode behaviour with a high rectification ratio
S Carmel, A Pon, R Ramesh, A Bhattacharyya
Physica E: Low-dimensional Systems and Nanostructures 114, 113630, 2019
42019
Analysis of 1/f and G–R noise in Phosphorene FETs
A Pon, M Ehteshamuddin, K Sheelvardhan, A Dasgupta
Solid-State Electronics 200, 108530, 2023
32023
Optimization of gate all-around junctionless transistor using response surface methodology
R Ramesh, A Pon, PD Babu, S Carmel, A Bhattacharyya
Silicon, 1-10, 2022
32022
Channel and gate engineered dielectric modulated asymmetric dual short gate TFET
SCAB R. Ramesh, A. Pon
IEEE Xplore, pp. 1-4., 2017
3*2017
Influence of temperature on p-GaN HEMT for high power application
N Geddam, B Snega, A Pon, A Bhattacharyya, R Ramesh
2020 5th International Conference on Devices, Circuits and Systems (ICDCS …, 2020
22020
Calculation of electronic and transport properties of phosphorene nanoribbons using DFT and semi empirical models
AS Carmel, A Pon, R Ramesh, A Bhattacharryya
2017 International Conference on Microelectronic Devices, Circuits and …, 2017
22017
Phosphorene-based intelligent nanosensor for wearable electronics applications
R Ramesh, A Bhattacharyya, A Pon, D Nirmal, J Ajayan
Handbook of Nanomaterials for Sensing Applications, 347-369, 2021
12021
Historical Development of MOS Technology to Tunnel FETs
S Manikandan, A Pon
Tunneling Field Effect Transistors, 29-52, 2023
2023
Investigation on Ambipolar Current Suppression in Tunnel FETs
M Ehteshamuddin, S Manikandan, A Pon
Tunneling Field Effect Transistors, 169-192, 2023
2023
Phosphorene Multigate Field-Effect Transistors for High-Frequency Applications
R Rathinam, A Pon, A Bhattacharyya
Sub-Micron Semiconductor Devices, 335-354, 2022
2022
Computational study of Phosphorene Nanoribbons (PNRs) Based PN Junction Diode with High Rectification Ratio
S Carmel, A Pon, R Rathinam, A Bhattacharyya
2019 IEEE International Conference on Electron Devices and Solid-State …, 2019
2019
Influence of Temperature on the Performance of Dual Gate Phosphorene TFET
A Pon, S Carmel, A Bhattacharyya, R Ramesh
2019 International Conference on Vision Towards Emerging Trends in …, 2019
2019
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Articles 1–20