| IR-drop analysis of hybrid bonded 3D-ICs with backside power delivery and μ-& n-TSVs G Sisto, B Chehab, B Genneret, R Baert, R Chen, P Weckx, J Ryckaert, ... 2021 IEEE International Interconnect Technology Conference (IITC), 1-3, 2021 | 17 | 2021 |
| 3D-optimized SRAM macro design and application to memory-on-logic 3D-IC at advanced nodes R Chen, P Weckx, SM Salahuddin, SW Kim, G Sisto, G Van Der Plas, ... 2020 IEEE International Electron Devices Meeting (IEDM), 15.2. 1-15.2. 4, 2020 | 16 | 2020 |
| Design and optimization of SRAM macro and logic using backside interconnects at 2nm node R Chen, G Sisto, A Jourdain, G Hiblot, M Stucchi, N Kakarla, B Chehab, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.4. 1-22.4. 4, 2021 | 11 | 2021 |
| Design enablement of fine pitch face-to-face 3D system integration using die-by-die place & route G Sisto, P Debacker, R Chen, G Van Der Plas, R Chou, E Beyne, ... 2019 International 3D Systems Integration Conference (3DIC), 1-4, 2019 | 11 | 2019 |
| Extended scale length theory targeting low-dimensional FETs for carbon nanotube FET digital logic design-technology co-optimization C Gilardi, B Chehab, G Sisto, P Schuddinck, Z Ahmed, O Zografos, Q Lin, ... 2021 IEEE International Electron Devices Meeting (IEDM), 27.3. 1-27.3. 4, 2021 | 6 | 2021 |
| Fine-pitch 3D system integration and advanced CMOS nodes: technology and system design perspective D Milojevic, G Sisto, G Van der Plas, E Beyne Design-Process-Technology Co-optimization XV 11614, 67-72, 2021 | 6 | 2021 |
| Block-level evaluation and optimization of backside PDN for high-performance computing at the A14 node G Sisto, R Preston, R Chen, G Mirabelli, A Farokhnejad, Y Zhou, I Ciofi, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 5 | 2023 |
| Disruptive technology elements, and rapid and accurate block-level performance evaluation for 3nm and beyond MH Na, D Jang, R Baert, S Sarkar, S Patli, O Zografos, B Chehab, ... 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021 | 5 | 2021 |
| Backside pdn and 2.5 d mimcap to double boost 2d and 3d ics ir-drop beyond 2nm node R Chen, G Sisto, M Stucchi, A Jourdain, K Miyaguchi, P Schuddinck, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 4 | 2022 |
| Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network R Chen, M Lofrano, G Mirabelli, G Sisto, S Yang, A Jourdain, F Schleicher, ... 2022 International Electron Devices Meeting (IEDM), 23.4. 1-23.4. 4, 2022 | 2 | 2022 |
| Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes G Sisto, R Chen, R Chou, G Van der Plas, E Beyne, R Metcalfe, ... 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2021 | 2 | 2021 |
| Backside Power Delivery: Game Changer and Key Enabler of Advanced Logic Scaling and New STCO Opportunities A Veloso, B Vermeersch, R Chen, P Matagne, MG Bardon, G Eneman, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 1 | 2023 |
| Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era G Sisto, O Zografos, B Chehab, N Kakarla, Y Xiang, D Milojevic, P Weckx, ... IEEE transactions on very large scale integration (VLSI) systems 30 (10 …, 2022 | 1 | 2022 |
| 3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling N Horiguchi, H Mertens, T Chiarella, S Demuynck, V Vega-Gonzalez, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | | 2023 |
| Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs M Naeim, H Yang, P Chen, R Bao, A Dekeyser, G Sisto, M Brunion, ... 2023 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2023 | | 2023 |
| System-level evaluation of 3D power delivery network at 2nm node G Sisto, R Chen, D Milojevic, O Zografos, P Weckx, G Hellings, J Ryckaert DTCO and Computational Patterning II 12495, 208-218, 2023 | | 2023 |
| Physical design level PPA evaluation of buried power rail at 2nm node G Sisto, O Zografos, P Weckx, G Hellings, J Ryckaert DTCO and Computational Patterning II 12495, 2023 | | 2023 |
| Ruthenium Metallization and Via Prefill for Electromigration Reliability Enhancement in Advanced Sub-3 nm Node Interconnects S Esposto, G Sisto, I Ciofi, D Milojevic, K Croes, H Zahedmanesh International Integrated Reliability Workshop IIRW 2023, 1-4, 2023 | | 2023 |
| Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection R Chen, G Sisto, O Zografos, D Milojevic, P Weckx, G Van der Plas, ... Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect …, 2022 | | 2022 |
| Digital IC design with sub-3nm CMOS technology and 3D integration: Pathfinding towards the enablement of emerging technologies G Sisto Université libre de Bruxelles, 2022 | | 2022 |
Dragomir MilojevicUniversité libre de BruxellesVerifierad e-postadress på ulb.ac.be
