Kaushik Ravindran
Kaushik Ravindran
National Instruments R&D
Verifierad e-postadress på ni.com
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First-order incremental block-based statistical timing analysis
C Visweswariah, K Ravindran, K Kalafala, SG Walker, S Narayan, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
Efficient parallelization of h. 264 decoding with macro block level scheduling
J Chong, N Satish, B Catanzaro, K Ravindran, K Keutzer
2007 IEEE international conference on multimedia and expo, 1874-1877, 2007
An automated exploration framework for FPGA-based soft multiprocessor systems
K Keutzer, K Ravindran, N Satish, Y Jin
2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software …, 2005
Multi-domain clock skew scheduling
K Ravindran, A Kuehlmann, E Sentovich
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
An FPGA-based soft multiprocessor system for IPv4 packet forwarding
K Ravindran, N Satish, Y Jin, K Keutzer
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
Np-click: A productive software development approach for network processors
N Shah, W Plishker, K Ravindran, K Keutzer
IEEE Micro 24 (5), 45-54, 2004
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors
N Satish, K Ravindran, K Keutzer
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Optimization of a data flow program based on access pattern information
G Wang, K Ravindran, R Limaye, G Yang, A Ghosal, HA Andrade, ...
US Patent 9,335,977, 2016
Scheduling task dependence graphs with variable task execution times onto heterogeneous multiprocessors
NR Satish, K Ravindran, K Keutzer
Proceedings of the 8th ACM international conference on Embedded software …, 2008
Developing programs in a graphical specification and constraint language
K Ravindran, G Yang, J Kornerup, IC Wong, JN Correll, MJ Trimborn, ...
US Patent 8,726,228, 2014
Developing programs for hardware implementation in a graphical specification and constraint language
K Ravindran, J Kornerup, R Limaye, G Yang, G Wang, JN Correll, ...
US Patent 8,887,121, 2014
Automated task allocation for network processors
W Plishker, K Ravindran, N Shah, K Keutzer
Network System Design Conference Proceedings, 235-245, 2004
Automatically Mapping Program Functions to Distributed Heterogeneous Platforms Based on Hardware Attributes and Specified Constraints
K Ravindran, HA Andrade, A Prasad, A Ghosal, TN Tran, R Limaye, ...
US Patent App. 15/470,374, 2017
Multi-domain clock skew scheduling
A Kuehlmann, K Ravindran, E Sentovich
US Patent 7,296,246, 2007
Correct and non-defensive glue design using abstract models
S Tripakis, H Andrade, A Ghosal, R Limaye, K Ravindran, G Wang, ...
2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on …, 2011
Developing programs for hardware implementation in a graphical specification and constraint language Via iterative estimation of performance or resource utilization
G Wang, JN Correll, SB Malik, HA Andrade, NG Petersen, R Limaye, ...
US Patent 8,719,774, 2014
Automated task allocation on single chip, hardware multithreaded, multiprocessor systems
W Plishker, K Ravindran, N Shah, K Keutzer
Workshop on Embedded Parallel Architectures (WEPA-1) 2, 14-20, 2004
Static dataflow with access patterns: semantics and analysis
A Ghosal, R Limaye, K Ravindran, S Tripakis, A Prasad, G Wang, TN Tran, ...
DAC Design Automation Conference 2012, 656-663, 2012
Scheduling tasks to maximize usage of aggregate variables in place
S Abu-Mahmeed, C McCosh, Z Budimlić, K Kennedy, K Ravindran, ...
International Conference on Compiler Construction, 204-219, 2009
Task allocation and scheduling of concurrent applications to multiprocessor systems
K Ravindran
University of California, Berkeley, 2007
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