| A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator G Wu, D Huang, J Li, P Gui, T Liu, S Guo, R Wang, Y Fan, S Chakraborty, ... Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2016 | 42 | 2016 |
| A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO S Guo, P Gui, T Liu, T Zhang, T Xi, G Wu, Y Fan, M Morgan IEEE Transactions on Circuits and Systems I: Regular Papers, 1-12, 2018 | 40 | 2018 |
| 10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS T Zhang, P Gui, S Chakraborty, T Liu, G Wu, P Moreira, F Tavernier IEEE, 2016 | 18 | 2016 |
| A Temperature Compensated Triple-Path PLL With KVCO Non-Linearity Desensitization Capable of Operating at 77 K T Liu, X Wang, R Wang, G Wu, T Zhang, P Gui IEEE Transactions on Circuits and Systems I: Regular Papers, 1-9, 2017 | 17* | 2017 |
| A low-voltage low-power 25 Gb/s clock and data recovery with equalizer in 65 nm CMOS S Guo, T Liu, T Zhang, T Xi, G Wu, P Gui, Y Fan, W Maung, M Morgan 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 307-310, 2015 | 12 | 2015 |
| Ultra-wideband loss of signal detector at a receiver in a high speed serializer/deserializer (SERDES) application S Zhan, T Liu, E Chen US Patent 9,252,928, 2016 | 8 | 2016 |
| A 1-16-Gb/s all-digital clock and data recovery with a wideband, high-linearity phase interpolator G Wu, D Huang, J Li, P Gui, T Liu, S Guo, R Wang, Y Fan, S Chakraborty, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015 | 7 | 2015 |
| A 2.56-Gb/s serial wireline transceiver that supports an auxiliary channel in 65-nm CMOS X Wang, T Liu, S Guo, MA Thornton, P Gui IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (1), 12-22, 2019 | 6 | 2019 |
| A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade C Chen, V Wallangen, D Gong, C Grace, Q Sun, D Guo, G Huang, S Kulis, ... Journal of Instrumentation 14 (07), C07005, 2019 | 6 | 2019 |
| Charge pump linearization technique for delta-sigma fractional-N synthesizers Z Yang, Liu, Tianwei US Patent 7,969,247, 2011 | 4 | 2011 |
| A 2.56 Gbps Asynchronous Serial Transceiver with Embedded 80 Mbps Secondary Data Transmission Capability in 65nm CMOS X Wang, T Liu, S Guo, MA Thornton, P Gui 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 360-363, 2018 | 2 | 2018 |
| 一种新型的低电压高速 CMOS 锁相环电荷泵 杨运福， 戴庆元， 刘天伟 微处理机 27 (3), 11-13, 2006 | 1 | 2006 |
| A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS S Guo, T Xi, G Wu, T Liu, T Zhang, P Gui, Y Fan, M Morgan 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | | 2014 |
| Ultra-wideband loss of signal detector at a receiver in a high speed serializer/deserializer (serdes) EC Sanyi Zhan, Tainwei Liu US Patent App. 20140192841 A1, 2014 | | 2014 |
