Ritesh Parikh
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Power-aware NoCs through routing and topology reconfiguration
R Parikh, R Das, V Bertacco
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
Comprehensive Online Defect Diagnosis in On-Chip Networks
A Ghofrani, R Parikh, S Shamshiri, A DeOrio, KT Cheng, V Bertacco
VLSI Test Symposium (VTS) 2012, 2012
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
R Parikh, V Bertacco
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
Formally Enhanced Runtime Verification to Ensure NoC Functional Correctness
R Parikh, V Bertacco
International Symposium on Microarchitecture (MICRO) 2011, 2011
Brisk and limited-impact NoC routing reconfiguration
D Lee, R Parikh, V Bertacco
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
High-radix on-chip networks with low-radix routers
A Jain, R Parikh, V Bertacco
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 289-294, 2014
A comparative performance evaluation of network-on-chip architectures under self-similar traffic
S Kundu, K Manna, S Gupta, K Kumar, R Parikh, S Chattopadhyay
2009 International Conference on Advances in Recent Technologies in …, 2009
Highly fault-tolerant NoC routing with application-aware congestion management
D Lee, R Parikh, V Bertacco
Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015
Functional Correctness for CMP Interconnects
R Abdel-Khalek, R Parikh, A DeOrio, V Bertacco
International Conference on Computer Design (ICCD) 2011, 2011
Resource conscious diagnosis and reconfiguration for noc permanent faults
R Parikh, V Bertacco
IEEE Transactions on Computers 65 (7), 2241-2256, 2016
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
R Parikh, V Bertacco
ACM Transactions on Embedded Computing Systems (TECS) 13 (3s), 1-30, 2014
Redeem: A heterogeneous distributed microarchitecture for energy-efficient reliability
B Mammo, R Parikh, V Bertacco
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
Power-Aware Multi-Level AND-XOR Network Synthesis
R Parikh, S Chattopadhyay
International Journal of Computers and Applications 33 (1), 22-28, 2011
NoCVision: A Network-on-Chip Dynamic Visualization Solution
V Gogte, D Lee, R Parikh, V Bertacco
Proceedings of the 8th International Workshop on Network on Chip …, 2015
Routing and Topology Reconfiguration for Networks-on-Chip’s Runtime Health.
R Parikh
Boosting the Performance of MapReduce Applications via Distributed Accelerators on a Chip-Multiprocessor
A Addisie, R Abdel-Khalek, R Parikh, V Bertacco
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Artiklar 1–16