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Juan Salamanca
Juan Salamanca
IC-UNICAMP
Verified email at ic.unicamp.br
Title
Cited by
Cited by
Year
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation
J Salamanca, JN Amaral, G Araujo
IEEE Transactions on Parallel and Distributed Systems 29 (2), 466-480, 2018
162018
Evaluating and improving thread-level speculation in hardware transactional memories
J Salamanca, JN Amaral, G Araujo
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2016
162016
Performance evaluation of thread-level speculation in off-the-shelf hardware transactional memories
J Salamanca, JN Amaral, G Araujo
European Conference on Parallel Processing, 607-621, 2017
52017
Loop-Carried Dependence Verification in OpenMP
J Salamanca, L Mattos, G Araujo
International Workshop on OpenMP, 87-102, 2014
52014
A Proposal for Supporting Speculation in the OpenMP taskloop Construct
J Salamanca, A Baldassin
International Workshop on OpenMP, 246-261, 2019
32019
Doacross parallelization based on component annotation and loop-carried probability
L Mattos, D Cesar, J Salamanca, JPL de Carvalho, M Pereira, G Araujo
2018 30th International Symposium on Computer Architecture and High …, 2018
22018
Using hardware transactional memory to implement speculative privatization in OpenMP
J Salamanca, A Baldassin
International Workshop on Languages and Compilers for Parallel Computing, 57-73, 2020
12020
Improving Speculative taskloop in Hardware Transactional Memory
J Salamanca, A Baldassin
International Workshop on OpenMP, 3-17, 2021
2021
Using Hardware Transactional Memory to Enable Speculative Trace Optimization
J Salamanca, JN Amaral, G Araujo
2015 International Symposium on Computer Architecture and High Performance …, 2015
2015
Thread-level speculation on hardware transactional memory architectures= Especulação de threads usando arquiteturas de memória transacional em hardware
JJ Salamanca Guillén
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