| CuMAPz: A tool to analyze memory access patterns in CUDA Y Kim, A Shrivastava Proceedings of the 48th design automation conference, 128-133, 2011 | 71 | 2011 |
| WCET-aware dynamic code management on scratchpads for software-managed multicores Y Kim, D Broman, J Cai, A Shrivastava Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 …, 2014 | 43 | 2014 |
| Precision timed infrastructure: Design challenges D Broman, M Zimmer, Y Kim, H Kim, J Cai, A Shrivastava, SA Edwards, ... Proceedings of the 2013 Electronic System Level Synthesis Conference (ESLsyn …, 2013 | 36 | 2013 |
| Memory performance estimation of CUDA programs Y Kim, A Shrivastava ACM Transactions on Embedded Computing Systems (TECS) 13 (2), 1-22, 2013 | 11 | 2013 |
| Splitting functions in code management on scratchpad memories Y Kim, J Cai, Y Kim, K Lee, A Shrivastava Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016 | 10 | 2016 |
| WCET-aware function-level dynamic code management on scratchpad memory Y Kim, D Broman, A Shrivastava ACM Transactions on Embedded Computing Systems (TECS) 16 (4), 1-26, 2017 | 7 | 2017 |
| Clock scheduling and cell library information utilization for power supply noise reduction YS Kim, SW Han, JH Kim JSTS: Journal of Semiconductor Technology and Science 9 (1), 29-36, 2009 | 6 | 2009 |
| WCET-aware stack frame management of embedded systems using scratchpad memories Y Kim, M Khayatian, A Shrivastava 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 4 | 2019 |
| WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems Y Kim Arizona State University, 2017 | 4 | 2017 |
| Branch penalty reduction on IBM cell SPUs via software branch hinting J Lu, Y Kim, A Shrivastava, C Huang Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011 | 4 | 2011 |
| Reducing code management overhead in software-managed multicores J Cai, Y Kim, Y Kim, A Shrivastava, K Lee Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 3 | 2017 |
| Power supply noise reduction by clock scheduling with gate-level current waveform estimation Y Kim, S Han, J Kim 2008 International SoC Design Conference 2, II-166-II-169, 2008 | 2 | 2008 |
| A second-order gate delay modeling method with an efficient sensitivity analysis S Han, Y Kim, W Choi, I Shin, Y Choi APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1008-1011, 2008 | | 2008 |
Aviral ShrivastavaArizona State UniversityVerified email at asu.edu
