| Factors that impact the critical charge of memory elements T Heijmen, D Giot, P Roche 12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006 | 173 | 2006 |
| Multiple cell upsets as the key contribution to the total SER of 65 nm CMOS SRAMs and its dependence on well engineering G Gasiot, D Giot, P Roche IEEE Transactions on Nuclear Science 54 (6), 2468-2473, 2007 | 172 | 2007 |
| Technology downscaling worsening radiation effects in bulk: SOI to the rescue P Roche, JL Autran, G Gasiot, D Munteanu 2013 IEEE International Electron Devices Meeting, 31.1. 1-31.1. 4, 2013 | 151 | 2013 |
| Impacts of front-end and middle-end process modifications on terrestrial soft error rate P Roche, G Gasiot IEEE Transactions on Device and Materials Reliability 5 (3), 382-396, 2005 | 119 | 2005 |
| Single event upset and multiple cell upset modeling in commercial bulk 65-nm CMOS SRAMs and flip-flops S Uznanski, G Gasiot, P Roche, C Tavernier, JL Autran IEEE Transactions on Nuclear Science 57 (4), 1876-1883, 2010 | 106 | 2010 |
| Analysis of multiple bit upsets (MBU) in CMOS SRAM O Musseau, F Gardic, P Roche, T Corbiere, RA Reed, S Buchner, ... IEEE Transactions on Nuclear Science 43 (6), 2879-2888, 1996 | 106 | 1996 |
| Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node P Roche, G Gasiot, K Forbes, V O'Sullivan, V Ferlet IEEE Transactions on Nuclear Science 50 (6), 2046-2054, 2003 | 104 | 2003 |
| Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs D Giot, P Roche, G Gasiot, JL Autran, R Harboe-Sorensen 2007 9th European Conference on Radiation and Its Effects on Components and …, 2007 | 101 | 2007 |
| A comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries T Heijmen, P Roche, G Gasiot, KR Forbes, D Giot IEEE Transactions on Device and Materials Reliability 7 (1), 84-96, 2007 | 85 | 2007 |
| A comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries T Heijmen, P Roche, G Gasiot, KR Forbes, D Giot IEEE Transactions on Device and Materials Reliability 7 (1), 84-96, 2007 | 85 | 2007 |
| Multiple-bit upset analysis in 90 nm SRAMs: Heavy ions testing and 3D simulations D Giot, P Roche, G Gasiot, R Harboe-Sorensen IEEE Transactions on Nuclear Science 54 (4), 904-911, 2007 | 84 | 2007 |
| Criterion for SEU occurrence in SRAM deduced from circuit and device simulations in case of neutron-induced SER T Merelle, H Chabane, JM Palau, K Castellani-Coulie, F Wrobel, F Saigné, ... IEEE transactions on nuclear science 52 (4), 1148-1155, 2005 | 82 | 2005 |
| Altitude and underground real-time SER characterization of CMOS 65 nm SRAM JL Autran, P Roche, S Sauze, G Gasiot, D Munteanu, P Loaiza, ... IEEE Transactions on Nuclear Science 56 (4), 2258-2266, 2009 | 75 | 2009 |
| A commercial 65nm CMOS technology for space applications: Heavy ion, proton and gamma test results and modeling P Roche, G Gasiot, S Uznanski, JM Daveau, J Torras-Flaquer, S Clerc, ... 2009 European Conference on Radiation and Its Effects on Components and …, 2009 | 69 | 2009 |
| Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology G Gasiot, D Giot, P Roche IEEE Transactions on Nuclear Science 53 (6), 3479-3486, 2006 | 69 | 2006 |
| SEU sensitivity of bulk and SOI technologies to 14-MeV neutrons G Gasiot, V Ferlet-Cavrois, J Baggio, P Roche, P Flatresse, A Guyot, ... IEEE Transactions on Nuclear Science 49 (6), 3032-3037, 2002 | 66 | 2002 |
| SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts G Gasiot, D Soussan, M Glorieux, C Bottoni, P Roche 2014 IEEE International Reliability Physics Symposium, SE. 6.1-SE. 6.5, 2014 | 55 | 2014 |
| Soft-error rate induced by thermal and low energy neutrons in 40 nm SRAMs JL Autran, S Serre, S Semikh, D Munteanu, G Gasiot, P Roche IEEE Transactions on Nuclear Science 59 (6), 2658-2665, 2012 | 55 | 2012 |
| 8.4 a 0.33 v/-40 c process/temperature closed-loop compensation soc embedding all-digital clock multiplier and dc-dc converter exploiting fdsoi 28nm back-gate biasing S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 53 | 2015 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 52 | 2014 |
Jean-Luc AutranProfessor, Aix-Marseille University & Université de RennesVerified email at univ-amu.fr
