Changhwan Shin
Changhwan Shin
Verified email at skku.edu
Title
Cited by
Cited by
Year
Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages
A Padilla, CW Yeung, C Shin, C Hu, TJK Liu
2008 IEEE International Electron Devices Meeting, 1-4, 2008
1742008
Negative capacitance in organic/ferroelectric capacitor to implement steep switching MOS devices
J Jo, WY Choi, JD Park, JW Shim, HY Yu, C Shin
Nano letters 15 (7), 4553-4556, 2015
1582015
Negative capacitance field effect transistor with hysteresis-free sub-60-mV/decade switching
J Jo, C Shin
IEEE Electron Device Letters 37 (3), 245-248, 2016
1552016
Study of random dopant fluctuation effects in germanium-source tunnel FETs
N Damrongplasit, C Shin, SH Kim, RA Vega, TJK Liu
IEEE transactions on electron devices 58 (10), 3541-3548, 2011
1272011
Study of random-dopant-fluctuation (RDF) effects for the trigate bulk MOSFET
C Shin, X Sun, TJK Liu
IEEE Transactions on Electron Devices 56 (7), 1538-1542, 2009
892009
Negative capacitance FinFET with sub-20-mV/decade subthreshold slope and minimal hysteresis of 0.48 V
E Ko, JW Lee, C Shin
IEEE Electron Device Letters 38 (4), 418-421, 2017
832017
Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap
X Sun, Q Lu, V Moroz, H Takeuchi, G Gebara, J Wetzel, S Ikeda, C Shin, ...
IEEE Electron Device Letters 29 (5), 491-493, 2008
752008
Vertical tunnel FET: Design optimization with triple metal-gate layers
E Ko, H Lee, JD Park, C Shin
IEEE Transactions on Electron Devices 63 (12), 5030-5035, 2016
552016
Effect of the Si/TiO2/BiVO4 Heterojunction on the Onset Potential of Photocurrents for Solar Water Oxidation
H Jung, SY Chae, C Shin, BK Min, OS Joo, YJ Hwang
ACS applied materials & interfaces 7 (10), 5788-5796, 2015
542015
Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs
X Sun, V Moroz, N Damrongplasit, C Shin, TJK Liu
IEEE transactions on electron devices 58 (10), 3294-3299, 2011
542011
Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node
C Shin, MH Cho, Y Tsukamoto, BY Nguyen, C Mazuré, B Nikolić, TJK Liu
IEEE Transactions on electron devices 57 (6), 1301-1309, 2010
532010
Ultra-thick semi-crystalline photoactive donor polymer for efficient indoor organic photovoltaics
SC Shin, CW Koh, P Vincent, JS Goo, JH Bae, JJ Lee, C Shin, H Kim, ...
Nano Energy 58, 466-475, 2019
512019
Study of high-k/metal-gate work-function variation using Rayleigh distribution
H Nam, C Shin
IEEE Electron Device Letters 34 (4), 532-534, 2013
472013
Variation-aware advanced CMOS devices and SRAM
C Shin
Springer, 2016
452016
Advanced MOSFET designs and implications for SRAM scaling
C Shin
UC Berkeley, 2011
432011
Steep switching devices for low power applications: Negative differential capacitance/resistance field effect transistors
E Ko, J Shin, C Shin
Nano Convergence 5 (1), 1-9, 2018
422018
Design optimization of multigate bulk MOSFETs
B Ho, X Sun, C Shin, TJK Liu
IEEE transactions on electron devices 60 (1), 28-33, 2012
402012
Sub-60-mV/decade negative capacitance FinFET with sub-10-nm hafnium-based ferroelectric capacitor
E Ko, H Lee, Y Goh, S Jeon, C Shin
IEEE Journal of the Electron Devices Society 5 (5), 306-309, 2017
352017
Specific Contact Resistivity Reduction Through Ar Plasma-Treated TiO2−xInterfacial Layer to Metal/Ge Contact
GS Kim, JK Kim, SH Kim, J Jo, C Shin, JH Park, KC Saraswat, HY Yu
IEEE Electron Device Letters 35 (11), 1076-1078, 2014
332014
Impact of temperature on negative capacitance field‐effect transistor
J Jo, C Shin
Electronics Letters 51 (1), 106-108, 2015
322015
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Articles 1–20