Saurabh Sinha
Saurabh Sinha
Principal Research Engineer, ARM Research
Verified email at arm.com
Title
Cited by
Cited by
Year
Exploring sub-20nm FinFET design with predictive technology models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
DAC Design Automation Conference 2012, 283-288, 2012
2862012
ASAP7: A 7-nm finFET predictive process design kit
LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ...
Microelectronics Journal 53, 105-115, 2016
1382016
Compact modeling of carbon nanotube transistor for early stage process-design exploration
A Balijepalli, S Sinha, Y Cao
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
922007
Correlated electron switch programmable fabric
L Shifren, G Yeric, S Sinha, B Cline, V Chandra
US Patent 10,056,143, 2018
692018
Tuning the permeability of permalloy films for on-chip inductor applications
T Dastagir, W Xu, S Sinha, H Wu, Y Cao, H Yu
Applied Physics Letters 97 (16), 162506, 2010
682010
Performance enhancement of on-chip inductors with permalloy magnetic rings
W Xu, S Sinha, T Dastagir, H Wu, B Bakkaloglu, DS Gardner, Y Cao, H Yu
IEEE Electron Device Letters 32 (1), 69-71, 2010
542010
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM
T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan
IEEE Electron Device Letters 38 (8), 1161-1164, 2017
452017
Improved frequency response of on-chip inductors with patterned magnetic dots
W Xu, S Sinha, F Pan, T Dastagir, Y Cao, H Yu
IEEE electron device letters 31 (3), 207-209, 2010
352010
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools
K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
342016
Physical design and FinFETs
R Aitken, G Yeric, B Cline, S Sinha, L Shifren, I Iqbal, V Chandra
Proceedings of the 2014 on International symposium on physical design, 65-68, 2014
332014
Compact model of carbon nanotube transistor and interconnect
S Sinha, A Balijepalli, Y Cao
IEEE transactions on electron devices 56 (10), 2232-2242, 2009
302009
Sub-100 μm scale on-chip inductors with CoZrTa for GHz applications
W Xu, H Wu, DS Gardner, S Sinha, T Dastagir, B Bakkaloglu, Y Cao, H Yu
Journal of Applied Physics 109 (7), 07A316, 2011
292011
Design benchmarking to 7nm with FinFET predictive technology models
S Sinha, B Cline, G Yeric, V Chandra, Y Cao
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
262012
Power benefit study of monolithic 3D IC at the 7nm technology node
K Chang, K Acharya, S Sinha, B Cline, G Yeric, SK Lim
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
252015
Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology
L Shifren, R Aitken, AR Brown, V Chandra, B Cheng, C Riddet, ...
IEEE Transactions on Electron Devices 61 (7), 2271-2277, 2014
252014
32-bit processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance
CS Lee, B Cline, S Sinha, G Yeric, HSP Wong
2016 IEEE International Electron Devices Meeting (IEDM), 28.3. 1-28.3. 4, 2016
222016
The past present and future of design-technology co-optimization
G Yeric, B Cline, S Sinha, D Pietromonaco, V Chandra, R Aitken
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013
222013
Near-threshold computing in FinFET technologies: Opportunities for improved voltage scalability
N Pinckney, L Shifren, B Cline, S Sinha, S Jeloka, RG Dreslinski, T Mudge, ...
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
202016
Simulation study of the impact of quantum confinement on the electrostatically driven performance of n-type nanowire transistors
Y Wang, T Al-Ameri, X Wang, VP Georgiev, E Towie, SM Amoroso, ...
IEEE Transactions on Electron Devices 62 (10), 3229-3236, 2015
192015
A simplified model of carbon nanotube transistor with applications to analog and digital design
S Sinha, A Balijepalli, Y Cao
9th International Symposium on Quality Electronic Design (isqed 2008), 502-507, 2008
192008
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