| Determining an effective stress level on a processor D Shapira, E Rotem, DR Moran US Patent 9,098,561, 2015 | 14 | 2015 |
| Power management based on real time platform power sensing D Shapira, AK Enamandram, D Cartagena, K Sistla, JP Rodriguez, ... US Patent 11,054,877, 2021 | 12 | 2021 |
| Hierarchical power management apparatus and method V Garg, A Varma, K Sistla, N Gupta, NS Baligar, S Wang, N Palit, T Kam, ... US Patent App. 17/033,753, 2022 | 10 | 2022 |
| Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance S Zobel, M Levit, E Rotem, E Weissmann, D Rajwan, D Shapira, ... US Patent 9,983,644, 2018 | 10 | 2018 |
| Balanced control of processor temperature N Rosenzweig, D Rajwan, D Shapira, N Shulman, T Ziv US Patent 9,791,904, 2017 | 10 | 2017 |
| Providing lifetime statistical information for a processor D Shapira, E Rotem, D Rajwan, N Shulman, E Natanzon, N Rosenzweig US Patent 9,904,339, 2018 | 9 | 2018 |
| Apparatus and method for controlling the reliability stress rate on a processor D Shapira, KV Sistla, E Rotem, N Shulman, S Zobel, A Chu US Patent 9,317,389, 2016 | 7 | 2016 |
| Apparatus and method for a user configurable reliability control loop D Shapira, KV Sistla, E Rotem, E Distefano, IIJG Hermerding, E Natanzon US Patent 10,289,514, 2019 | 6 | 2019 |
| Multi-level loops for computer processor control D Rajwan, E Rotem, E Weissmann, AN Ananthakrishnan, D Shapira US Patent 10,216,246, 2019 | 6 | 2019 |
| Method and apparatus for providing power state information using in-band signaling D Rajwan, D Shapira, I Feit, N Shulman, T Kuzi, E Weissmann, T Ziv, ... US Patent 10,474,216, 2019 | 3 | 2019 |
| Multi-level loops for computer processor control D Rajwan, E Rotem, E Weissmann, AN Ananthakrishnan, D Shapira US Patent 11,481,013, 2022 | 1 | 2022 |
| Multi-level loops for computer processor control D Rajwan, E Rotem, E Weissmann, AN Ananthakrishnan, D Shapira US Patent 10,678,319, 2020 | 1 | 2020 |
| Multi-level loops for computer processor control D Rajwan, E Rotem, E Weissmann, AN Ananthakrishnan, D Shapira US Patent App. 18/048,593, 2023 | | 2023 |
| Platform slicing of central processing unit (CPU) resources C Macnamara, JJ Browne, T Kantecki, D Hunt, A Burakov, S Makineni, ... US Patent 11,567,556, 2023 | | 2023 |
| Power management based on real time platform power sensing D Shapira, A Enamandram, D Cartagena, K Sistla, JP Rodriguez, ... US Patent App. 17/354,821, 2021 | | 2021 |
| Dynamic maximum frequency limit for processing core groups AH Al-Rawi, F Ardanaz, JM Eastep, D Shapira, K Sistla, N Gupta, ... US Patent 11,144,085, 2021 | | 2021 |
| Balancing power between discrete components in a compute node PK Kandula, EJ DeHaemer, D Shapira, R Nagappan, V Garg, F Keceli, ... US Patent App. 17/191,564, 2021 | | 2021 |
| System, apparatus and method for controlling a processor based on effective stress information E Rotem, E Natanzon, D Rajwan, E Weissmann, D Shapira, LP Looi, ... US Patent 11,029,744, 2021 | | 2021 |
| Generation of processor interrupts using averaged data XC Man, JJ Shrall, D Ganapathy, D Shapira US Patent 11,016,916, 2021 | | 2021 |
| Generation of processor interrupts using averaged data XC Man, JJ Shrall, D Ganapathy, D Shapira US Patent 10,657,083, 2020 | | 2020 |
