| Design of two-dimensional zero phase FIR fan filters via the McClellan transform EZ Psarakis, VG Mertzios, GP Alexiou IEEE Transactions on Circuits and Systems 37 (1), 10-16, 1990 | 63 | 1990 |
| Target localization utilizing the success rate in infrared pattern recognition N Petrellis, N Konofaos, GP Alexiou IEEE Sensors Journal 6 (5), 1355-1364, 2006 | 44 | 2006 |
| Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs) T Karoubalis, GP Alexiou, N Kanopoulos Proceedings of EURO-DAC. European Design Automation Conference, 282-287, 1995 | 23 | 1995 |
| A new serial/parallel two's complement multiplier for VLSI digital signal processing GP Alexiou, N Kanopoulos International journal of circuit theory and applications 20 (2), 209-214, 1992 | 17 | 1992 |
| A core generator for arithmetic cores and testing structures with a network interface D Bakalis, KD Adaos, D Lymperopoulos, M Bellos, HT Vergos, GP Alexiou, ... Journal of Systems Architecture 52 (1), 1-12, 2006 | 13 | 2006 |
| Estimation of a target position based on infrared pattern reception quality N Petrellis, N Konofaos, GP Alexiou IETE Technical Review 27 (1), 36-45, 2010 | 7 | 2010 |
| Using future position restriction rules for stabilizing the results of a noise-sensitive indoor localization system N Petrellis, N Konofaos, GP Alexiou Optical Engineering 46 (6), 067202-067202-11, 2007 | 5 | 2007 |
| Multiprocessor vision system NG Bourbakis, M Papazoglou, G Alexiou Microprocessors and Microsystems 14 (9), 573-582, 0 | 4* | |
| Utilizing infrared pattern recognition features for indoor localization validated by future position restrictions N Petrellis, N Konofaos, GP Alexiou Proc. 2nd IET Int. Conf. Intelligent Environments (IE’06), 307-311, 2006 | 3 | 2006 |
| A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier T Karoubalis, K Adaos, GP Alexiou, N Kanopoulos International journal of circuit theory and applications 23 (6), 587-598, 1995 | 3 | 1995 |
| Multi field SRAM access via intra-encoders and crossbar addressing scheme T Simopoulos, L Spyridopoulos, GP Alexiou, N Konofaos 2017 6th International Conference on Modern Circuits and Systems …, 2017 | 2 | 2017 |
| Implementation of a 256x8 Sector Size SRAM grid with memory write speedup on CeidMem library T Simopoulos, T Haniotakis, GP Alexiou 2016 5th International Conference on Modern Circuits and Systems …, 2016 | 2 | 2016 |
| Crossbar sector addressing scheme on SRAMs L Spyridopoulos, N Konofaos, T Simopoulos, GP Alexiou 2017 Panhellenic Conference on Electronics and Telecommunications (PACET), 1-4, 2017 | 1 | 2017 |
| Low power built-in self-test schemes for array and booth multipliers D Bakalist, X Kavousianos, HT Vergos, D Nikolos, GP Alexiou VLSI Design 12 (3), 431-448, 2001 | 1 | 2001 |
| Efficient methods for preprocessing Greek Letters NG Bourbakis, P Pintelas, G Alexiou, S Zeinis Digital Techniques, Elsevier Sc, Pub, 229-234, 1985 | 1 | 1985 |
| Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model T Simopoulos, GP Alexiou, T Haniotakis Journal of Circuits, Systems and Computers 28 (supp01), 1940008, 2019 | | 2019 |
| Rapid Static Memory Read-Write for Energy-Aware Applications T Simopoulos, T Haniotakis, GP Alexiou, N Sklavos High-Speed and Lower Power Technologies, 253-268, 2018 | | 2018 |
| A 1Kx32 bit WDSRAM page with rapid write access T Simopoulos, T Haniotakis, GP Alexiou 2018 13th International Conference on Design & Technology of Integrated …, 2018 | | 2018 |
| Welcome to ISQED 2010 K Gadepally, L Immaneni, P Chatterjee, G Alexiou, A Iranmanesh 2010 11th International Symposium on Quality Electronic Design (ISQED), iii-iii, 2010 | | 2010 |
| A dual rail circuits synthesis environment for the implementation of multiple output boolean functions T Karoubalis, GP Alexiou, N Kanopoulos International journal of circuit theory and applications 26 (4), 329-342, 1998 | | 1998 |
