The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH Computer Architecture News 39 (2), 1-7, 2011 | 5118 | 2011 |
Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016 | 2611 | 2016 |
GARNET: A detailed on-chip network model inside a full-system simulator N Agarwal, T Krishna, LS Peh, NK Jha 2009 IEEE international symposium on performance analysis of systems and …, 2009 | 848 | 2009 |
Maeri: Enabling flexible dataflow mapping over dnn accelerators via reconfigurable interconnects H Kwon, A Samajdar, T Krishna ACM SIGPLAN Notices 53 (2), 461-475, 2018 | 316 | 2018 |
Scale-sim: Systolic cnn accelerator simulator A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018 | 224 | 2018 |
Sigma: A sparse and irregular gemm accelerator with flexible interconnects for dnn training E Qin, A Samajdar, H Kwon, V Nadella, S Srinivasan, D Das, B Kaul, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 186 | 2020 |
Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 155 | 2019 |
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering BK Daya, CHO Chen, S Subramanian, WC Kwon, S Park, T Krishna, ... 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 150 | 2014 |
Breaking the on-chip latency barrier using SMART T Krishna, CHO Chen, WC Kwon, LS Peh 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 136 | 2013 |
SMART: A single-cycle reconfigurable NoC for SoC applications CHO Chen, S Park, T Krishna, S Subramanian, AP Chandrakasan, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 338-343, 2013 | 121 | 2013 |
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI S Park, T Krishna, CH Chen, B Daya, A Chandrakasan, LS Peh Proceedings of the 49th Annual Design Automation Conference, 398-405, 2012 | 115 | 2012 |
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication T Krishna, LS Peh, BM Beckmann, SK Reinhardt Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 113 | 2011 |
NoC with near-ideal express virtual channels using global-line communication T Krishna, A Kumar, P Chiang, M Erez, LS Peh 2008 16th IEEE Symposium on High Performance Interconnects, 11-20, 2008 | 100 | 2008 |
On-chip networks NE Jerger, T Krishna, LS Peh Synthesis Lectures on Computer Architecture 12 (3), 1-210, 2017 | 89 | 2017 |
Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks L Yang, Z Yan, M Li, H Kwon, L Lai, T Krishna, V Chandra, W Jiang, Y Shi 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 70 | 2020 |
Swift: A swing-reduced interconnect for a token-based network-on-chip in 90nm cmos T Krishna, J Postman, C Edmonds, LS Peh, P Chiang 2010 IEEE International Conference on Computer Design, 439-446, 2010 | 67 | 2010 |
Rethinking NoCs for spatial neural network accelerators H Kwon, A Samajdar, T Krishna 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2017 | 65 | 2017 |
Characterizing the deployment of deep neural networks on commercial edge devices R Hadidi, J Cao, Y Xie, B Asgari, T Krishna, H Kim 2019 IEEE International Symposium on Workload Characterization (IISWC), 35-48, 2019 | 64 | 2019 |
The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 63 | 2020 |
Smart: Single-cycle multihop traversals over a shared network on chip T Krishna, CHO Chen, WC Kwon, LS Peh IEEE micro 34 (3), 43-56, 2014 | 58 | 2014 |