Oana Boncalo
Oana Boncalo
Assistant Professor at Computer Engineering Department, University Politehnica Timisoara
Verifierad e-postadress på cs.upt.ro
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Design issues and implementations for floating-point divide–add fused
A Amaricai, M Vladutiu, O Boncalo
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (4), 295-299, 2010
FPGA design of high throughput LDPC decoder based on imprecise offset min-sum decoding
T Nguyen-Ly, K Le, F Ghaffari, A Amaricai, O Boncalo, V Savin, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
An FPGA sliding window-based architecture harris corner detector
A Amaricai, CE Gavriliu, O Boncalo
2014 24th International Conference on Field Programmable Logic and …, 2014
Analysis and design of cost-effective, high-throughput LDPC decoders
TT Nguyen-Ly, V Savin, K Le, D Declercq, F Ghaffari, O Boncalo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 508-521, 2017
Non-surjective finite alphabet iterative decoders
TT Nguyen-Ly, K Le, V Savin, D Declercq, F Ghaffari, O Boncalo
2016 IEEE International Conference on Communications (ICC), 1-6, 2016
Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing
O Boncalo, A Amaricai, A Hera, V Savin
2014 24th International Conference on Field Programmable Logic and …, 2014
Probabilistic gate level fault modeling for near and sub-threshold CMOS circuits
A Amaricai, S Nimara, O Boncalo, J Chen, E Popovici
2014 17th Euromicro Conference on Digital System Design, 473-479, 2014
Variable-node-shift based architecture for probabilistic gradient descent bit flipping on QC-LDPC codes
K Le, D Declercq, F Ghaffari, L Kessal, O Boncalo, V Savin
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2183-2195, 2017
FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization
S Nimara, O Boncalo, A Amaricai, M Popa
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
Using simulated fault injection for fault tolerance assessment of quantum circuits
O Boncalo, M Udrescu, L Prodan, M Vladutiu, A Amaricai
40th Annual Simulation Symposium (ANSS'07), 213-220, 2007
Cost effective FPGA probabilistic fault emulation
O Boncalo, A Amaricai, C Spagnol, E Popovici
2014 NORCHIP, 1-4, 2014
Design of addition and multiplication units for high performance interval arithmetic processor
A Amaricai, M Vladutiu, L Prodan, M Udrescu, O Boncalo
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-4, 2007
Memory efficient FPGA implementation for flooded LDPC decoder
A Amaricai, O Boncalo, I Mot
2015 23rd Telecommunications Forum Telfor (TELFOR), 500-503, 2015
Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays
A Amaricai, O Boncalo, CE Gavriliu
IET Computers & Digital Techniques 8 (4), 187-197, 2014
Design of floating point units for interval arithmetic
A Amaricai, M Vladutiu, O Boncalo
2009 Ph. D. Research in Microelectronics and Electronics, 12-15, 2009
Design for dependability in emerging technologies
L Prodan, M Udrescu, O Boncalo, M Vladutiu
ACM Journal on Emerging Technologies in Computing Systems (JETC) 3 (2), 6-es, 2007
Memory trade-offs in layered self-corrected min-sum LDPC decoders
O Boncalo, A Amaricai, PF Mihancea, V Savin
Analog Integrated Circuits and Signal Processing 87 (2), 169-180, 2016
Template-based QC-LDPC decoder architecture generation
O Boncalo, PF Mihancea, A Amaricai
2015 10th International Conference on Information, Communications and Signal …, 2015
A moving window architecture for a hw/sw codesign based canny edge detection for fpga
A Amaricai, O Boncalo, M Iordate, B Marinescu
2012 28th International Conference on Microelectronics Proceedings, 393-396, 2012
Exploiting parallelism in double path adders' structure for increased throughput of floating point addition
A Amaricai, M Vladupiu, L Prodan, M Udrescu, O Boncalo
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
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