Debapriya Chatterjee
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GPU computing gems emerald edition
WMW Hwu
Elsevier, 2011
401*2011
Event-driven gate-level simulation with GP-GPUs
D Chatterjee, A DeOrio, V Bertacco
Proceedings of the 46th Annual Design Automation Conference, 557-562, 2009
1092009
High-performance gate-level simulation with GP-GPUs
D Chatterjee, A DeOrio, V Bertacco
GPU Computing Gems Emerald Edition, 343-364, 2011
802011
Simulation-based signal selection for state restoration in silicon debug
D Chatterjee, C McCarter, V Bertacco
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 595-601, 2011
752011
SAGA: SystemC acceleration on GPU architectures
S Vinco, V Bertacco, D Chatterjee, F Fummi
DAC Design Automation Conference 2012, 115-120, 2012
432012
Gate-level simulation with GPU computing
D Chatterjee, A Deorio, V Bertacco
ACM Transactions on Design Automation of Electronic Systems (TODAES) 16 (3 …, 2011
212011
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
N Bombieri, S Vinco, V Bertacco, D Chatterjee
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012
172012
Checking architectural outputs instruction-by-instruction on acceleration platforms
D Chatterjee, A Koyfman, R Morad, A Ziv, V Bertacco
DAC Design Automation Conference 2012, 955-961, 2012
162012
On the use of GP-GPUs for accelerating compute-intensive EDA applications
V Bertacco, D Chatterjee, N Bombieri, F Fummi, S Vinco, AM Kaushik, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
132013
Gate-Level Logic Simulator Using Multiple Processor Architectures
V Bertacco, D Chatterjee, A Deorio, THEROFTHEUOF MICHIGAN
US Patent 8,738,349, 2014
102014
High performance gate-level simulation with gp-gpu computing
V Bertacco, D Chatterjee
Proceedings of 2011 International Symposium on VLSI Design, Automation and …, 2011
82011
EQUIPE: Parallel equivalence checking with GP-GPUs
D Chatterjee, V Bertacco
2010 IEEE International Conference on Computer Design, 486-493, 2010
82010
Study of the potential of alternative crops by integration of multisource data using a neuro‐fuzzy technique
A Sarkar, A Majumdar, S Chatterjee, D Chatterjee, SS Ray, B Kartikeyan
International Journal of Remote Sensing 29 (19), 5479-5493, 2008
72008
Approximating checkers for simulation acceleration
B Mammo, D Chatterjee, D Pidan, A Nahir, A Ziv, R Morad, V Bertacco
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 153-158, 2012
62012
Activity-based refinement for abstraction-guided simulation
D Chatterjee, V Bertacco
2009 IEEE International High Level Design Validation and Test Workshop, 146-153, 2009
42009
ArChiVED: Architectural checking via event digests for high performance validation
CH Hsu, D Chatterjee, R Morad, R Ga, V Bertacco
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
32014
Addressing verification challenges of heterogeneous systems based on IBM POWER9
K. D. Schubert, S. S. Abrar, D. Averill, E. Bauman, A. C. Brown, R. Cash, D ...
IBM Journal of Research and Development 62 (4), 2018
22018
Circuit design verification in a hardware accelerated simulation environment using breakpoints
R Batra, D Chatterjee, CR Jones, CM Riedl, JA SCHUMANN, KE YOKUM
US Patent 9,939,487, 2018
12018
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms
D Chatterjee, B Mammo, D Lee, R Gal, R Morad, A Nahir, A Ziv, ...
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 311-317, 2013
12013
Method and system for detection of thread stall
O Bajaj, K Barnett, D Chatterjee, B Cockcroft, J Hawkins, LG Hehenberger, ...
US Patent App. 16/831,055, 2020
2020
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