| Inverse slope isolation and dual surface orientation integration MG Sadaka, D Eades, J Mogab, BY Nguyen, MO Zavala, GS Spencer US Patent 7,575,968, 2009 | 453 | 2009 |
| Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region M Sadaka, I Radu US Patent 8,461,017, 2013 | 268 | 2013 |
| Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking I Radu, D Landru, G Gaudin, G Riou, C Tempesta, F Letertre, L Di Cioccio, ... 2010 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2010 | 244 | 2010 |
| Direct bonding for wafer level 3D integration L Di Cioccio, I Radu, P Gueguen, M Sadaka 2010 IEEE International Conference on Integrated Circuit Design and …, 2010 | 233 | 2010 |
| Building blocks for wafer-level 3D integration M Sadaka, L Di Cioccio Solid State Technology 52 (10), 20-24, 2009 | 227 | 2009 |
| Low temperature direct wafer to wafer bonding for 3D integration G Gaudin, G Riou, M Sadaka, K Winstel, E Kinser 3D Systems Integration Conference (3DIC), IEEE, 16-18, 2010 | 226 | 2010 |
| Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods M Sadaka, I Radu, D Landru US Patent 8,716,105, 2014 | 153 | 2014 |
| Bonding surfaces for direct bonding of semiconductor structures M Sadaka US Patent 8,697,493, 2014 | 145 | 2014 |
| Advanced RF enhancement-mode FETs with improved gate properties MJ Martinez, E Schirmann, OL Hartin, CG Rampley, MG Sadaka, ... US Patent 6,893,947, 2005 | 132 | 2005 |
| Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods M Sadaka, I Radu, D Landru, L Di Cioccio US Patent 8,501,537, 2013 | 130 | 2013 |
| Semiconductor device structure and method therefor TR White, AL Barr, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean US Patent 7,226,833, 2007 | 126 | 2007 |
| Semiconductor structure having strained semiconductor and method therefor AL Barr, D Jovanovic, BY Nguyen, MG Sadaka, VY Thean, TR White US Patent 7,205,210, 2007 | 87 | 2007 |
| Method for forming a semiconductor device having a strained channel and a heterojunction source/drain VY Thean, MG Sadaka, TR White, AL Barr, VR Kolagunta, BY Nguyen, ... US Patent 7,018,901, 2006 | 78 | 2006 |
| Low RC product transistors in SOI semiconductor process AL Barr, OO Adetutu, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean, ... US Patent 7,037,795, 2006 | 69 | 2006 |
| Method of making a dual strained channel semiconductor device MG Sadaka, AL Barr, D Jovanovic, BY Nguyen, VY Thean, SG Thomas, ... US Patent 7,282,402, 2007 | 66 | 2007 |
| High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation B Brar, W Ha, M Sadaka, C Nguyen US Patent App. 11/711,340, 2007 | 64 | 2007 |
| Dual surface SOI by lateral epitaxial overgrowth BA Winstead, O Zia, MG Sadaka, MK Orlowski US Patent 7,435,639, 2008 | 63 | 2008 |
| Double gate device having a heterojunction source/drain and strained channel VY Thean, MG Sadaka, TR White, AL Barr, VR Kolagunta, BY Nguyen, ... US Patent 7,067,868, 2006 | 55 | 2006 |
| Twisted dual-substrate orientation (DSO) substrates TR White, L Mathew, BY Nguyen, Z Shi, VY Thean, MG Sadaka US Patent 7,803,670, 2010 | 46 | 2010 |
| Semiconductor device structure TR White, AL Barr, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean US Patent 7,781,840, 2010 | 41 | 2010 |
