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James Goodman
James Goodman
Professor Emeritus of Computer Science, University of Wisconsin-Madison
Verifierad e-postadress på cs.wisc.edu
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Using cache memory to reduce processor-memory traffic
JR Goodman
Proceedings of the 10th annual international symposium on Computer …, 1983
7911983
Speculative lock elision: Enabling highly concurrent multithreaded execution
R Rajwar, JR Goodman
Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001
6592001
Memory bandwidth limitations of future microprocessors
D Burger, JR Goodman, A Kägi
ACM SIGARCH Computer Architecture News 24 (2), 78-89, 1996
6401996
Cache consistency and sequential consistency
JR Goodman
University of Wisconsin-Madison Department of Computer Sciences, 1991
4711991
Transactional lock-free execution of lock-based programs
R Rajwar, JR Goodman
ACM SIGOPS Operating Systems Review 36 (5), 5-17, 2002
4482002
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
JR Goodman, MK Vernon, PJ Woest
Proceedings of the third international conference on Architectural support …, 1989
4331989
Code scheduling and register allocation in large basic blocks
JR Goodman, WC Hsu
ACM International Conference on Supercomputing 25th Anniversary Volume, 88-98, 1988
3791988
The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor
JR Goodman, PJ Woest
ACM SIGARCH Computer Architecture News 16 (2), 422-431, 1988
2751988
Hypertree: A multiprocessor interconnection topology
Goodman, C Sequin
IEEE Transactions on Computers 100 (12), 923-933, 1981
2351981
PIPE: a VLSI decoupled architecture
JR Goodman, J Hsieh, K Liou, AR Pleszkun, PB Schechter, HC Young
ACM SIGARCH Computer Architecture News 13 (3), 20-27, 1985
1731985
Concurrent execution of critical sections by eliding ownership of locks
R Rajwar, JR Goodman
US Patent 7,120,762, 2006
1632006
System and method for performing incremental register checkpointing in transactional memory
MS Moir, D Dice, DS Nussbaum, JR Goodman
US Patent 8,560,816, 2013
1622013
Billion-transistor architectures
D Burger, JR Goodman
Computer 30 (09), 46-49, 1997
1571997
Coherency for multiprocessor virtual address caches
JR Goodman
ACM SIGARCH Computer Architecture News 15 (5), 72-81, 1987
1431987
Improving CC-NUMA performance using instruction-based prediction
S Kaxiras, JR Goodman
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
1321999
The impact of pipelined channels on k-ary n-cube networks
SL Scott, JR Goodman
IEEE Transactions on Parallel and Distributed Systems 5 (1), 2-16, 1994
1321994
Instruction cache replacement policies and organizations
Goodman
IEEE Transactions on Computers 100 (3), 234-241, 1985
1161985
The declining effectiveness of dynamic caching for general-purpose microprocessors
DC Burger, JR Goodman, A Kagi
University of Wisconsin-Madison Department of Computer Sciences, 1995
1141995
Efficient synchronization: Let them eat QOLB
A Kägi, D Burger, JR Goodman
Proceedings of the 24th annual international symposium on Computer …, 1997
1131997
Performance of the SCI Ring
SL Scott, JR Goodman, MK Vernon
Proceedings of the 19th Annual International Symposium on Computer …, 1992
1111992
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Artiklar 1–20