| Managing shared last-level cache in a heterogeneous multicore processor V Mekkat, A Holey, PC Yew, A Zhai Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 116 | 2013 |
| HAccRG: Hardware-Accelerated Data Race Detection in GPUs A Holey, V Mekkat, A Zhai | 21* | |
| Accelerating data race detection utilizing on-chip data-parallel cores V Mekkat, A Holey, A Zhai International Conference on Runtime Verification, 201-218, 2013 | 14 | 2013 |
| Performance characterization of data mining benchmarks V Mekkat, R Natarajan, WC Hsu, A Zhai Proceedings of the 2010 Workshop on Interaction between Compilers and …, 2010 | 13 | 2010 |
| Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor V Mekkat, O Margulis, JM Agron, E Schuchman, S Winkel, Y Wu, ... US Patent 9,996,356, 2018 | 12 | 2018 |
| Performance-energy considerations for shared cache management in a heterogeneous multicore processor A Holey, V Mekkat, PC Yew, A Zhai ACM Transactions on Architecture and Code Optimization (TACO) 12 (1), 1-29, 2015 | 12 | 2015 |
| Auxiliary Cache for Reducing Instruction Fetch and Decode Bandwidth Requirements JM Agron, A Merrick, V Mekkat US Patent App. 15/087,786, 2017 | 11 | 2017 |
| Eliminating redundant stores using a protection designator and a clear designator V Mekkat, Y Wu, S Winkel, O Margulis US Patent 10,540,178, 2020 | 6 | 2020 |
| EFFECTIVENESS OF COMPILER-DIRECTED PREFETCHING ON DATA MINING BENCHMARKS R NATARAJAN, V MEKKAT, WEIC HSU, A ZHAI Journal of Circuits, Systems, and Computers 21 (02), 2012 | 3 | 2012 |
| Technology For Providing Memory Atomicity With Low Overhead M Shevgoor, MJ Dechene, V Mekkat, JM Agron, Z Zhang US Patent App. 16/367,409, 2020 | 2 | 2020 |
| Technology For Optimizing Memory-To-Register Operations VT Mekkat, SCA Winkel, RBR Chowdhury US Patent App. 17/304,775, 2022 | 1 | 2022 |
| System, method, and apparatus for enhanced pointer identification and prefetching S Subramoney, S Shwartsman, A Nori, S Balachandran, E Shtiegmann, ... US Patent 11,080,194, 2021 | 1 | 2021 |
| Instruction and Logic for Total Store Elimination V Mekkat, O Margulis, CT Chou, Y Wu US Patent App. 15/175,899, 2017 | 1* | 2017 |
| Shift-folding for efficient load coalescing in a binary translation based processor V Mekkat, X Chen, M Shevgoor US Patent 10,915,320, 2021 | | 2021 |
| Method and apparatus for supporting speculative memory optimizations V Mekkat, M Dechene, Z Zhang, J Faistl, J Lee, HJ Ko, S Winkel, ... US Patent 10,853,078, 2020 | | 2020 |
| Hybrid atomicity support for a binary translation based microprocessor V Mekkat, JM Agron, Y Wu US Patent 10,296,343, 2019 | | 2019 |
| Register reclamation V Mekkat, J Lee, Y Wu US Patent 10,235,177, 2019 | | 2019 |
| Supporting binary translation alias detection in an out-of-order processor V Mekkat, MJ Dechene, Z Zhang, J Agron, S Winkel US Patent 10,228,956, 2019 | | 2019 |
| Methods and apparatus to optimize instructions for execution by a processor V Mekkat, G Venkatasubramanian, HH Chen US Patent 9,916,164, 2018 | | 2018 |
| Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform O Margulis, S Ahuja, P Xekalakis, P Yongjun, V Mekkat, I Yanover, ... US Patent 9,710,389, 2017 | | 2017 |
Anup HoleyNvidiaVerified email at nvidia.com
