| Source-level timing annotation for fast and accurate TLM computation model generation KL Lin, CK Lo, RS Tsay 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 235-240, 2010 | 58 | 2010 |
| Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model CK Lo, RS Tsay 2009 Asia and South Pacific Design Automation Conference, 558-563, 2009 | 20 | 2009 |
| Cycle-count-accurate processor modeling for fast and accurate system-level simulation CK Lo, LC Chen, MH Wu, RS Tsay 2011 Design, Automation & Test in Europe, 1-6, 2011 | 11 | 2011 |
| Locality-Aware Scheduling for Stencil Code in Halide CKL Shih-Wei Liao, Sheng-Jun Tsai, Chieh-Hsun Yang ICPP Workshop, 2016 | 5* | 2016 |
| Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis ML Li, CK Lo, LC Chen, HJ Huang, JC Yeh, RS Tsay US Patent App. 13/398,083, 2013 | 5 | 2013 |
| Cycle-Count-Accurate (CCA) Processor Modeling for System-Level Simulation CK Lo, LC Chen, MH Wu, RS Tsay US Patent App. 13/008,921, 2012 | 4 | 2012 |
| System and method for managing static divergence in a SIMD computing architecture CK Lo, SW Liao, HAN Cheng-Ting, D Ju US Patent 9,921,838, 2018 | 3 | 2018 |
| Automatic generation of high-speed accurate tlm models for out-of-order pipelined bus CK Lo, ML Li, LC Chen, YS Lu, RS Tsay, HY Huang, JC Yeh ACM Transactions on Embedded Computing Systems (TECS) 13 (1s), 1-25, 2013 | 3 | 2013 |
| System for Simulating Processor Power Consumption and Method of the Same CM Lee, CK Lo, MH Wu, RS Tsay US Patent App. 12/716,446, 2011 | 3 | 2011 |
| A Cycle Count Accurate TLM bus modeling approach ML Li, CK Lo, LC Chen, JC Yeh, RS Tsay 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 1-4, 2013 | 1 | 2013 |
| A formal full bus TLM modeling for fast and accurate contention analysis ML Li, CK Lo, LC Chen, HJ Huang, JC Yeh, RS Tsay Proc. 17th Workshop Synth. Syst. Integr. Mixed Inf. Technol., 7-10, 2012 | 1 | 2012 |
| Automatic TLM Model Generation for Cycle-Count-Accurate Bus Simulation RST C.-K. Lo, M.-L. Li, S.-Y. Chen, J.-C. Yeh the Work in Progress session at Design Automation Conference (DAC), San …, 2012 | | 2012 |
| Fast and Accurate TLM Computation Model Generation Using Source-Level Timing Annotation KL Lin, PJ Lin, CK Lo, RS Tsay | | |
Jen-Chieh (J.-C.) YehR&D, QualcommVerifierad e-postadress på larc.ee.nthu.edu.tw
