Polychronis Xekalakis
Polychronis Xekalakis
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Title
Cited by
Cited by
Year
Using predictivemodeling for cross-program design space exploration in multicore systems
S Khan, P Xekalakis, J Cavazos, M Cintra
16th International Conference on Parallel Architecture and Compilation …, 2007
692007
Eliminating redundant fragment shader executions on a mobile gpu via hardware memoization
JM Arnau, JM Parcerisa, P Xekalakis
ACM SIGARCH Computer Architecture News 42 (3), 529-540, 2014
562014
Combining thread level speculation helper threads and runahead execution
P Xekalakis, N Ioannou, M Cintra
Proceedings of the 23rd international conference on Supercomputing, 410-420, 2009
422009
Boosting mobile GPU performance with a decoupled access/execute fragment processor
JM Arnau, JM Parcerisa, P Xekalakis
ACM SIGARCH Computer Architecture News 40 (3), 84-93, 2012
412012
Applying decay to reduce dynamic power in set-associative caches
G Keramidas, P Xekalakis, S Kaxiras
International Conference on High-Performance Embedded Architectures and …, 2007
332007
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
S Kaxiras, P Xekalakis
Proceedings of the 2004 international symposium on Low power electronics and …, 2004
302004
TEAPOT: a toolset for evaluating performance, power and image quality on mobile graphics systems
JM Arnau, JM Parcerisa, P Xekalakis
Proceedings of the 27th international ACM conference on International …, 2013
272013
Parallel frame rendering: Trading responsiveness for energy on a mobile gpu
JM Arnau, JM Parcerisa, P Xekalakis
Proceedings of the 22nd international conference on Parallel architectures …, 2013
262013
Ascib: Adaptive selection of cache indexing bits for removing conflict misses
A Ros, P Xekalakis, M Cintra, ME Acacio, JM García
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
222012
Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region
R Martinez, EG Codina, P Lopez, MT Lapuerta, P Xekalakis, G Tournavitis, ...
US Patent 10,013,326, 2018
212018
Toward a more accurate understanding of the limits of the TLS execution paradigm
N Ioannou, J Singer, S Khan, P Xekalakis, P Yiapanis, A Pocock, G Brown, ...
IEEE International Symposium on Workload Characterization (IISWC'10), 1-12, 2010
202010
A simple mechanism to adapt leakage-control policies to temperature
S Kaxiras, P Xekalakis, G Keramidas
ISLPED'05. Proceedings of the 2005 International Symposium on Low Power …, 2005
172005
Method and apparatus for controlling a mxcsr
G Magklis, JM Codina, CB Zilles, M Neilly, S Samudrala, AM Vicente, ...
US Patent App. 13/995,416, 2013
92013
Handling branches in TLS systems with multi-path execution
P Xekalakis, M Cintra
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
92010
Adaptive selection of cache indexing bits for removing conflict misses
A Ros, P Xekalakis, M Cintra, ME Acacio, JM Garcia
IEEE Transactions on Computers 64 (6), 1534-1547, 2014
82014
Hardware apparatuses and methods to fuse instructions
PP Lai, TN Sondag, S Winkel, P Xekalakis, E Schuchman, J Iyer
US Patent 10,324,724, 2019
72019
Profitability-based power allocation for speculative multithreaded systems
P Xekalakis, N Ioannou, S Khan, M Cintra
2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010
72010
Instruction and Logic for Loop Stream Detection
P Xekalakis, JD Collins, S Ahuja
US Patent App. 14/580,498, 2016
62016
Mixed speculative multithreaded execution models
P Xekalakis, N Ioannou, M Cintra
ACM Transactions on Architecture and Code Optimization (TACO) 9 (3), 1-26, 2012
62012
Method and apparatus for implementing a dynamic out-of-order processor pipeline
DM Khartikov, N Neelakantam, JH Kelm, P Xekalakis
US Patent 9,612,840, 2017
52017
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Articles 1–20